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I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx wh

• duskwuff 8y ago
  Intel/Altera has HLS tools as well: https://www.altera.com/products/design-software/high-level-design/intel-hls-compiler/overview.html https://www.altera.com/products/design-software/high-level-d...
  • ktta 8y ago
    Well there you go. So GP's concerns are largely addressed. Intel can just work on this tooling, and people who are going to use HDL are going to continue using them.
    • slivym 8y ago
      Good idea in theory, in practice it's a shit show. The current level of language support is "As long as you know how to write what you want in HDL, then you can write some C that uses custom pragmas and design patterns and attributes that will badly reproduce what you could have written in HDL in half the time".
• slrz 8y ago
  > I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. These (almost by necessity) make you write code that doesn't look like any other C code. You can't just use some pre-existing C library and compile it to use FPGA resources. At that point, why not go a step further and just use a proper HDL?
  • ktta 8y ago
    Because although HDL doesn't look difficult syntax wise, it requires a very good understanding of logic gates. People need to pretty much take a course in digital design to be able to write something meaningful. It took me a while to grok HDL and write working code (good, maintainable code aside) even though I took digital design courses.
    • SlowRobotAhead 8y ago
      HDL ISNT CODE. FPGAs don’t get firmware. HDL is a description of hardware.
      • deleted 8y ago
        [deleted]
      • ktta 8y ago
        There's no need for all caps. HDL can be referred to as code. And I do know what HDL is and what FPGAs are, thank you.
        • SlowRobotAhead 8y ago
          >HDL can be referred to as code. No, it can't. That's why the caps are there and I'm sticking to it. You basically justified it ;) Code is something that you design to run sequentially. HDL is a description of gates and logic that runs all at the same time. If you wanted to argue that the bitstream is firmware - that's a tougher discussion.
          • perl4ever 8y ago
            If code is inherently sequential, do you think that there is no such thing as "code" in functional programming languages?
  • imtringued 8y ago
    >At that point, why not go a step further and just use a proper HDL? You're assuming that you're starting with an FPGA only project. In reality most projects that are going to be accellerated with these Xeon+FPGA systems is existing software where only a handful of hotspots will have be ported to the limited C language which is significantly less effort than rewriting the entire algorithm in HDL.
• typon 8y ago
  Altera/Intel has had OpenCL support for years now
  • ktta 8y ago
    OpenCL support is different from this.
    • typon 8y ago
      Its a different approach to HLS. Arguably much better than the Vivado approach
• aseipp 8y ago
  Intel recently released their own High Level Synthesis compiler for Quartus; like HLx, it's free and you can use it now on whatever device you want. You still have to do the interconnection to the CPU, if you have one. Unlike Xilinx, though, Intel (very very recently) just started offering their OpenCL-for-FPGA SDK for free, and it works on most of their device families, including Arria/Xeon and Cyclone/ARM. I always found it disappointing that the OpenCL SDKs were normally licensed, since they're more-or-less a logical extension of HLS support. So that's nice of Intel. They don't have any equivalent to Xilinx SDSoC though, but for datacenter targets they're shipping a different set of SDKs anyway (called "OPAE"), so maybe in the future they'll build something on top of the OPAE and OpenCL support (e.g. single-source model, like Sycl)