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One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag need
by kev009 8y ago
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that reality, and their product development arm seems too taxed to bridge the gap.
- sannee 8y ago> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?
- analognoise 8y agoWe get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
- akhilcacharya 8y agoHow do you define "bank"?
- maroonmed 8y agotree fiddy * 10^3
- jolmg 8y agoGetting paid bank means getting paid a lot of money. EDIT: You may also hear the phrase "making bank" to mean making (earning, not printing) a lot of money.
- grandmczeb 8y agoI think they were probably looking for a salary range.
- jolmg 8y agolol, you might be right. I thought it was an honest question from someone of a different native tongue.
- bitcoinmoney 8y agoI get paid 130k with a phd EE from tier 3 with <3 years industry experience. If you want to get in get ECE and study computer architecture and RTL. I am doing hardware modeling to predict future performance. It’s difficult to get in the industry from a tier 3 w/o experience but it’s worth it. My counterparts in FAANG are no doubt getting 300k/year. Sometimes I think maybe I should leetcode and get a software job @ FAANG because HW is difficult.
- akhilcacharya 8y agoall of my offers out of undergrad were more than that and I’m considered below average ¯\_(ツ)_/¯
- vba 8y agointerested to hear what bank is here too
- wahern 8y ago> it's key IP, you'd be stupid to outsource that That doesn't usually stop companies. At best it creates an opening for new companies to recapture some high-value markets once the dust from the off-shoring stampede settles.
- Tade0 8y agoWould you like to share how does one get into this line of work? I don't suppose there's an appropriate tutorial on egghead.io.
- kev009 8y agoThe standard path is more trodden than software development jobs -- ECE grad at a school with a good program.
- epmaybe 8y agoI know I took a digital logic course and did some fpga implementations in it, man that was hard. I am petrified of having to deal with HDL in the near future for my research, maybe I'll take a class or something.
- SlowRobotAhead 8y agoIn school they make you do it the hard way. I find verilog to be very similar to my process of how I write embedded C code.... short version is if you can make block diagrams and write good C, you can learn verilog.
- phendrenad2 8y agoIf you want to learn, there’s a ton of free training on the major vendor’s sites (Intel FPGA and Xilinx), and a development board with everything you need might run you a few hundred. But I don’t know what your job prospects would be without a degree in EE/CompE or experience in the hardware industry...
- aylons 8y agoHey, thank you for that. I really needed this motivation at this point in my life as an EE (RF, RTL and PCB level).
- schappim 8y agoHow would you recommend getting into the field?
- mozumder 8y agoElectrical Engineering college degree. That's the only option. I've never seen non-college degree electrical engineers.
- SlowRobotAhead 8y agoAllow me to introduce myself... not really becsuse anoniminity. But I’m effectively an EE at my company with no degree. Hardware, firmware, software, sourcing, production, validation/testing, and low volume assembly, all self taught. I’ll grt into FPGA when I have a use for it, but it certainly won’t be FFTs and DSPs but still. I’m glad I don’t have to job surf, it would be hard without paper, but my experience would be very valuable in my tiny field.
- mozumder 8y agoFor sure technicians that do these are a thing for finishing work, who may have AS degrees instead of BS EE. I've worked with them as well. They were always referred to as technicians that EE's hand-off more of the board-level debugging to (or even GDS II for ASIC design..). The core datapath processing algorithms were always done by EE's, though.
- monocasa 8y agoI'm another one. Embedded Engineer, no degree, works on core datapath and high level design, in addition to debug work.
- chocolatebunny 8y agoWe outsourced HDL validation.
- arkj 8y agoIt does get outsourced. I worked on a team that did a dsp/crypto multi core chip. The funny part is 90% of the team has now moved to US because they got paid better.
- kev009 8y agoI work on operating systems, which is similarly niche (but probably overall easier to learn and low risk vs fabbing ASICs) an it is very bi-modal. Sr. circuit designers can write their ticket, but you have a lot of warm bodies surrounding them at large companies.
- bitcoinmoney 8y agoHi, does your team have an opening? I work on performance modeling and am always curious if I could make the jump to low-level system software and learn a ton of stuff for a while.
- ksec 8y agosay EE/embedded space people are paid the same as average Javascript-slinging frontend dev, would you call this paid well?
- rjsw 8y agoLearning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.
- obl 8y agoHDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just compiler errors it's pretty bad compared to software.
- jsbto 8y agoHave to agree this is a major pain point for wider adoption. The current tools are mainly developed by a few big EDA vendors. I'm hoping, through the growth of open hardware communities, we'll start to see more friendly tools making progress.
- rwmj 8y agoLuckily there is (slow) progress on making good open source tools[1]. The Xilinx 7-series FPGAs were recently reverse-engineered too[2]. [1] https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-on-the-ice40-hx8k-fpga-breakout-board-part-1/ https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-... [2] https://github.com/SymbiFlow/prjxray https://github.com/SymbiFlow/prjxray
- craigjb 8y agoI’ve started using SpinalHDL, https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL. It’s a Scala DSL that spits out Verilog or VHDL for traditional synthesis tools. But, unlike Chisel or MyHDL, in my opinion it’s a great experience. And, now it has seamless integration with Verilator for simulation, and the open-source Verilator project is very capable—they claim it beats commercial simulators: https://www.veripool.org/wiki/verilator https://www.veripool.org/wiki/verilator. Since Scala is quite a bit faster than Python, the simulations run much faster than something like Cocotb too! I have my hobby project in SpinalHDL up at https://craigjb.com https://craigjb.com Edit: also, GTKWave is pretty good! It’s a simple and straightforward waveform viewer that works on all platforms.
- pkaye 8y agoI guess that is what you get when the entire software engineering field turns to "Javascript and a distributed database" as a solution to everything. There is a lot more out there and people should spend the time learning it.
- ktta 8y agoI wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.
- duskwuff 8y agoIntel/Altera has HLS tools as well: https://www.altera.com/products/design-software/high-level-design/intel-hls-compiler/overview.html https://www.altera.com/products/design-software/high-level-d...
- ktta 8y agoWell there you go. So GP's concerns are largely addressed. Intel can just work on this tooling, and people who are going to use HDL are going to continue using them.
- slivym 8y agoGood idea in theory, in practice it's a shit show. The current level of language support is "As long as you know how to write what you want in HDL, then you can write some C that uses custom pragmas and design patterns and attributes that will badly reproduce what you could have written in HDL in half the time".
- slrz 8y ago> I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. These (almost by necessity) make you write code that doesn't look like any other C code. You can't just use some pre-existing C library and compile it to use FPGA resources. At that point, why not go a step further and just use a proper HDL?
- ktta 8y agoBecause although HDL doesn't look difficult syntax wise, it requires a very good understanding of logic gates. People need to pretty much take a course in digital design to be able to write something meaningful. It took me a while to grok HDL and write working code (good, maintainable code aside) even though I took digital design courses.
- bonestamp2 8y ago> that bag needs people that write HDL and understand computer architecture to make good use of Over time I suppose they could have some machine learning that automatically configures the FPGA based on which programs you are running and the types of computations they have historically used.
- londons_explore 8y agomachine learning that automatically writes HDL programs to match functionality of x86 programs and are more efficient when executed on an FPGA than a general purpose CPU haven't yet been invented... Nor do I think they will be invented soon. Machine learning is bad at doing discrete things, bad at things requiring zero mistakes, and bad at problems for which the answer can't be perfectly verified (due to needing to solve the halting problem).
- petra 8y agoI think spiralgen can also do FPGA(or could do if needed), i.e. automatically generate highly optimized numerical code. http://www.spiralgen.com/ http://www.spiralgen.com/
- elteto 8y agoThere’s a pretty cool story about using evolutionary algorithms to program an FPGA for a specific task: https://www.damninteresting.com/on-the-origin-of-circuits https://www.damninteresting.com/on-the-origin-of-circuits. Probably not ML in the sense you were talking but very cool nonetheless. In the end the final result was hyperoptimized FPGA code that only ran on a specific board and used a bunch of nonsensical structures that seemed to be doing nothing, yet would stop the circuit from working if removed!
- qubex 8y agoI remember this, thanks for brining it up,:I had read it years ago and it always haunted me. The evolved solution involved using only 37 out of the 100 gates available, no clock, and some units were logically disconnected yet disabling them caused the chip to fail at its task, indicating it was relying on EM effects particular to the chip. Truly amazing (and perhaps a bit creepy too).
- sriku 8y agoThe FPGAs are programmable using OpenCL. That counts? https://www.altera.com/products/design-software/embedded-software-developers/opencl/overview.html https://www.altera.com/products/design-software/embedded-sof...
- angry_octet 8y agoI don't know if I'd call that programmable, isn't it just sequencing work to predefined logic blocks? Can you do things that were not contemplated by the opencl design?
- blackflame7000 8y agoOpenCL provides a standardization for interacting with accelerators. It is up to the manufacturers of FPGAs to adopt the OpenCL standard. For a while, Nvidia didn't get on board because they already had CUDA and felt OpenCL was letting ATI back in the game. Xilinx makes good learner FPGAs that are compatible with the OpenCL standard.
- shawnee_ 8y ago> little by way of tool chain integration Have a look at nGraph: http://ngraph.nervanasys.com/docs/latest/optimize/generic.html#ngraph-enabled-intel-xeon http://ngraph.nervanasys.com/docs/latest/optimize/generic.ht... Co-design for hardware+software is tough, for sure. But the reality is that hardware has to be present to build the software on top of it. People need something to play with. So the "bag on the side" of FPGAs here is kind of like Lego blocks for cache / acceleration. If you are running a DNN for inference, for example, cache is usually your bottleneck. Rent GPUs to train the model, figure out your bottleneck, and build your own isolated and local system for the "expensive lot of folks" to create the valuable IP.
- bobdole1234 8y agoThey've got an OpenCL SDK for it now, that brings it under the same interface that a lot of folks have been using for the Phi and other many core tech Intel has been pushing for HPC. It's not really that hard to get rolling at this point.
- mozumder 8y agoIt's really up to Intel to start funding education for architecture and HDL design.
- pasbesoin 8y agoI don't know whether it was deliberate, but I rather like that as a word: Flailure. (Although pronunciation and perception of it are not the easiest.) A lot of flailing about, as the ship goes down. (Speaking simply generally, about this "word". Not about the topic(s) in this thread.)
- srum 8y agoI'm not even sure they're going to let you program the FPGA drectly (with HDL)? I expect the main workflow will be using OpenCL to offload arbitrary work to the coprocessor along with a few Intel-provided modules capable of common tasks. The great thing about having the FPGA on-die via UPI is that the cache-coherency, decreased latency and massive bandwidth will allow much more granular offloading of work. This is as compared with PCIe coprocessor where it only makes sense to offload larger chunks of work and minimise the communication and data passing between the two. The greater the granularity of work that we can offload, the more viable the OpenCL/high-level synthesis/heterogeneous computing type stuff will be, as it will integrate more seamlessly into existing software development methods. This is the holy grail at the moment for FGPA vendors: to get to the point where software developers can program them on their own. As to your point though I guess we'll find out soon what the dev tools for this will actually look like.
- slivym 8y agoUsing OpenCL to program an FPGA is a significantly more difficult task than programming in HDL. Atleast for what would be relevant to a Xeon co-processor. The OpenCL flow is just terrible at getting to the performance levels you need to realistically offload anything from a Xeon. Intel are certainly working on it, but that's not a realistic proposition for the next 5 years, and if the Xeon+FPGA isn't already successful in that time frame, it'll be canned long before OpenCL is a solution. From what I've seen the only applications for this will be pre-canned FPGA images that were written in-house by Intel for things like encryption or FEC.
- clouddrover 8y agoVideo encoding would be another good application for the FPGA.
- slivym 8y agoI'm not so sure - it's a fantastic fit for GPUs, FPGAs make sense for stream processing for video encoding - but that's more of a discrete device play where you can plug the video feeds directly into the FPGA daughter board.