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Wow. I still remember being amazed when micron widths came out. 7nm is close to a miracle. Semiconductor manufacturing improvements like this really have enabl
by rb808 9y ago
Wow. I still remember being amazed when micron widths came out. 7nm is close to a miracle.
Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades.
- digi_owl 9y agoIn a sense it has been the "free lunch" of the industry, much like stored energy in hydrocarbons has been for manufacturing in general. But the supposed exponential curve that stock markets loves to salivate about seems to once again turn into an S curve.
- burnte 9y agoThere isn't any feature of the transistors taht are 7nm wide, the smallest feature IIRC is the interconnect, which is about 30n-40nm. "7nm" is marketing wankery. https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process
- Havoc 9y agoWell that's annoying. How is anyone supposed to judge anything if they just make numbers up?
- deleted 9y ago[deleted]
- andrewcchen 9y agoSmallest feature size no longer correlates with transistor density in recent years. So manufacturers just use the number to convey increases in transistor density. See https://en.wikichip.org/wiki/technology_node#History https://en.wikichip.org/wiki/technology_node#History
- elihu 9y agoI think bits of SRAM per unit of area is a benchmark that some people use, as it corresponds to something that's meaningful and measurable.
- kkmx 9y agoThat's a problematic metric as well because we don't know how much area the assist circuit takes up. Modern high-density SRAM cells cannot operate as is, they need an assist circuit to compensate for variations. For example for Intel's 10nm SRAM, they claim 77% area effiency (https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/5/ https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-inte...). But without those values, just bits/mm2 or so is problematic.
- astrodust 9y agoThe problem is even that is flawed as things are going three dimensional.
- indiv0 9y agoSo just start measuring in bits of SRAM per unit of volume?
- btian 9y agoHopefully their customers are more sophisticated than designing their chip based on a single number.
- quickben 9y agoWell, after a while or is sort of public knowledge that 10nm Intel is about the same as 12nm AMD, etc. But yes, the industry needs standardized advertising practices badly.
- abakker 9y ago>standardized advertising practices Oh man, I wish this would happen in any industry...sadly, advertising doesn't seem to see any benefit. Why standardize when you can differentiate?
- tfha 9y agoUh, it's the other way around. 10nm Intel is 7nm global foundries. 22nm Intel is superior to 14nm global foundries. Intel is the one that doesn't fudge their numbers.
- Valmar 9y agoEven Intel's numbers are just marketing, however. Everyone is fudging the numbers... SemiWiki has a good overview of Intel 10nm vs GF 7nm: https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge.html https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-...
- makomk 9y agoFor a while I think it was the other way around: Intel's processes were, in practice, actually substantially less dense than their competitors at the same nominal process node size.
- km3k 9y agoIntel still fudges their numbers. They just fudge their numbers less than everyone else.
- Valmar 9y agoHow so? The numbers don't seem to have much relation at all with all of the real process node numbers.
- km3k 9y agoThat's why they do it. The sizes of Intel's 10nm is similar to or slightly smaller than everyone else's 7nm. Compare https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process and https://en.wikichip.org/wiki/10_nm_lithography_process https://en.wikichip.org/wiki/10_nm_lithography_process .
- rb808 9y agoThanks, kinda ruined my day but I learned something.
- FPGAhacker 9y agoNot quite accurate. There are a number of dimensions involved. Interconnect is definitely not the smallest. This article show some examples: https://www.semiwiki.com/forum/content/3046-new-frontiers-scan-diagnosis.html https://www.semiwiki.com/forum/content/3046-new-frontiers-sc...
- fspeech 9y agoIf you look at the SRAM bit cells, they halved in area from 28nm to 14nm, and halved again from 14nm to 7nm. This is likely due to metal interconnects or other features only halving in spacing going from 28nm process to 7nm. So the scaling almost appears to apply to only one dimension (full linear scaling of two dimensions would have quartered the cell area at each step resulting in a 16-fold total reduction). But it is still scaling nevertheless.
- baybal2 9y agoWait for 3d sram
- typon 9y agoThere are different features sizes in the Z direction and different feature sizes in the XY plane. When it comes to XY, the smallest features size is probably the gate length. When it comes to Z, the gate oxide width is probably the smallest at 1-2nm. We have something called atomic layer deposition which gives control over single atomic layer thicknesses.
- CamperBob2 9y agoI've always assumed that "XX nm" doesn't represent the geometry of any particular feature of the end product, but something related to the wavelength of the radiation used for the imaging process. Maybe it corresponds to the principle emission line of the light source (synchrotron?) In spectral terms, 7 nm is near the border between hard UV radiation and soft X-rays.
- awalton 9y agoThis is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI https://www.youtube.com/watch?v=5yTARacBxHI - it's both fascinating and terrifying the trouble that EUV brings) and mirrors since pretty much all matter is opaque to EUV light. It's a bit maddening to think that features that much smaller than the wavelength of light used can be patterned with that light source, but we've made a science out of it over the past decade with multipatterning and immersion lithography.
- CamperBob2 9y agoSo, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength? I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.
- kurthr 9y agoIt's worse than that... there's not jist an industry group (ITRS), there's also the foundries making it up themselves. They're buying similar equipment and selling similar transistor densities (except for Intel which has finer geometries and higher densities for a given node), but few are directly compatible on density, clock-rate, or power consumption after 28nm. https://en.m.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductors https://en.m.wikipedia.org/wiki/International_Technology_Roa... Scalling really started falling apart in the late 90s around .25u, and then (incidentally) about the time CPU MHZ stopped scaling... by 65nm both gate and transistor length got wonky. Then after 28nm they moved to fin-FETs and multi-patterning making comparisons even more difficult. https://semiengineering.com/a-node-by-any-other-name/ https://semiengineering.com/a-node-by-any-other-name/
- deleted 9y ago[deleted]
- agumonkey 9y agoThis talk host said he doesn't believe 5nm will crack (unless major electronics breakthrough) https://www.youtube.com/watch?v=JpgV6rCn5-g&t=1136s https://www.youtube.com/watch?v=JpgV6rCn5-g&t=1136s
- deleted 9y ago[deleted]
- manaxi 9y ago> Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades. I would argue that for software it had the opposite effect, and has led to layers upon layers of crap. No need to ever fix that when you can rely on the next cpu being twice as fast.
- hexane360 9y agoDon't forget that optimization also costs time. Performance improvements just shifted the equilibrium between optimization and output. In the world where every programmer was forced to optimize their code, we'd have a lot less code.
- freeone3000 9y agoFrom your lips to God's ears.