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TSMC Kicks Off Volume Production of 7nm Chips
- shepting 8y agoIt's just stunning how they have been able to achieve 7nm features. With a 193nm wavelength laser no less.
- dbcooper 8y ago7nm is really just a node name. Gate length is probably about 20nm. Still very impressive though!
- dogma1138 8y agoThe gate pitch is 54mm for TSMC and 56nm for Global Foundries @ 7nm.
- AnimalMuppet 8y agoWell... the article didn't say what the line width, say, actually is. It just said that the process is labeled 7nm, which doesn't necessarily correspond to any features actually being 7nm in size. It just means it's that much smaller than the previous process. Don't get me wrong, it's still amazing, and the line widths are still going to be much less than 193 nm. I just wish they'd say what some standard feature size actually is.
- dogma1138 8y agoIt’s not 7nm in any feature size it’s seceral times that. It’s achievable usually with multiple patterning and submersion 193nm wavelength in vacuum which goes to about 145 in water and they likely are using something other than water and you also have temperature which affects the refractive index.
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- awalton 8y agoYeah, you should take the fact they're not using EUV as the tremendous boulder of salt that it is: these are actually 10nm parts. Node names continue to be washed into Megahertz War-style naming schemes. TSMC's process lines up pretty well with Intel's published numbers for their P1274 10nm process (Contacted Gate Pitch T & I: 54 nm, Minimum Metal Pitch T: 40nm I: 36 nm, High-Density SRAM bitcell size T: 0.027 µm^2 I: 0.0312 µm^2, etc). What we've learned out of all of this is that Intel's struggles to push tooling towards EUV have benefited the industry at wide, as everyone's spent so much effort there that existing processes and tooling has become cheaper and faster to iterate. They've certainly fallen behind their all-time lead of almost two process generations, but they still appear to be about a generation (18-ish months) ahead of TSMC by published numbers. But, who actually cares about the numbers, Marketing says 7nm so it's 7nm.
- Already__Taken 8y agoThere's a big difference when you compare making 7nm features with about 100 process steps whereas EUV are doing it in like 4 steps.
- tfha 8y agoEUV is still going to be 60+ steps.
- deepnotderp 8y ago1. Not really 7nm, only the fin width is ~7nm, metals, etc are more like 54nm. 2. Immersion lithography (water as refractive index) + multiple patterning + computational lithography.
- vardump 8y agoI wonder how reliable and durable 7nm chips will be. We might start to see chip failures even after a few years of use. https://semiengineering.com/transistor-aging-intensifies-10nm/ https://semiengineering.com/transistor-aging-intensifies-10n...
- FPGAhacker 8y agoGood question. Node size used to have a pretty firm definition, but it's malleable these days. Regardless of the absolute number, you can think of it as defining the smallest width of pencil you are used to make a drawing with. You can still use fatter pencils, and in many cases you would want to... shading in a large area for example. But having the smaller pencil lets you put in finer details. Some thing just won't work if they are too small though, so even though you have a fine sharp pencil available to use, somethings will not change. Regarding reliability over time, electromigration is the only thing I know of in a typical IC that causes degradation. It is affected by the size of conductors, so potentially things could get worse. It's a well understood phenomenon though so it's usually mitigated by design rules. Non volatile memories have their own degradation problems.
- Lind5 8y agoThere's no shortage of issues https://semiengineering.com/unsolved-litho-issues-at-7nm/ https://semiengineering.com/unsolved-litho-issues-at-7nm/ https://semiengineering.com/chip-aging-accelerates/ https://semiengineering.com/chip-aging-accelerates/
- rb808 8y agoWow. I still remember being amazed when micron widths came out. 7nm is close to a miracle. Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades.
- digi_owl 8y agoIn a sense it has been the "free lunch" of the industry, much like stored energy in hydrocarbons has been for manufacturing in general. But the supposed exponential curve that stock markets loves to salivate about seems to once again turn into an S curve.
- burnte 8y agoThere isn't any feature of the transistors taht are 7nm wide, the smallest feature IIRC is the interconnect, which is about 30n-40nm. "7nm" is marketing wankery. https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process
- Havoc 8y agoWell that's annoying. How is anyone supposed to judge anything if they just make numbers up?
- deleted 8y ago[deleted]
- andrewcchen 8y agoSmallest feature size no longer correlates with transistor density in recent years. So manufacturers just use the number to convey increases in transistor density. See https://en.wikichip.org/wiki/technology_node#History https://en.wikichip.org/wiki/technology_node#History
- elihu 8y agoI think bits of SRAM per unit of area is a benchmark that some people use, as it corresponds to something that's meaningful and measurable.
- jannes 8y agoDid any chip vendor announce 7nm chips yet? Or is this still secret?
- tux3 8y agoAMD's Zen2, which should come in or around 2019, will be on GloFo's 7nm. I believe TSMC will use 7nm for some memory and mobile applications. As for Intel their largely accepted equivalent to other foundries' 7nm is their 10nm, which is introduced in Cannon Lake/Ice Lake.
- tim333 8y agoAlso "Apple's 'A12' chip reportedly in production using 7nm"... "destined for 2018 iPhone models."
- mappu 8y agoIt's widely reported that the Snapdragon 855 will be on 7nm.
- srcmap 8y agoThere a quite a bit of them already - just google it: https://www.google.com/search?q=7nm+tapeout+press+release&client=firefox-b-1&ei=ftPfWo6IPMiF0wLNk7_YCg&start=10&sa=N&biw=632&bih=651 https://www.google.com/search?q=7nm+tapeout+press+release&cl... AMD, GPU, FPGA, etc.
- OhDagny 8y agoA 30% possible clock frequency increase? That is pretty big compared to other node shrinks, isn't it?
- nullnilvoid 8y agoInteresting time. This is the first time TSMC leads Intel in terms of node features if I remember correctly.
- bigtones 8y agoI have a question - why does the fab machine lithographic printing etch out a half a chip on the edge of the wafer like in the article picture. I presume the wafers are a standard 300mm size, so is it just because the designers were too lazy to remove the half chips on the edges from their mask template designs ?
- rb808 8y agoAha I had a question too why wafers are round. The answer is Crystals form in a cylinder then sliced. https://en.wikipedia.org/wiki/Wafer_(electronics)#Formation https://en.wikipedia.org/wiki/Wafer_(electronics)#Formation. Sorry it doesn't answer your question but helped me. :)
- tropo 8y agoYou could slice a cylinder the other way. That would give you rectangles, with the short dimension varying. I'm not so sure you'd save any space, but recycling the unused portion might be more reasonable to do.
- plv7 8y agoThe manufacturing process for semiconductors uses a standardized wafer size (in a given fab) so everything can be automated and simplified as far as possible. Having even something like just two wafer sizes makes a lot of the tooling/storage/transfer more complicated and expensive, so it's best to stick to one size and shape. In order to have uniform rectangular slices of the silicon crystal, you'd have to slice off horizontal cylinder segments. And that would defeat the purpose because if you just used circular wafers you'd have been able to get a couple dies out of that area.
- neltnerb 8y agoThe problem is that it is a single crystal of silicon. To keep it atomically flat you cannot cut it at any angle. You must cut it across the axis the crystal grows in or the surface will be rough and the wafer will likely crack in half in a stiff breeze. I suppose you could go for some more on-axis cuts, but the crystal planes are pretty restrictive on what you can do. You'd end up having super long and narrow pieces and such. http://www.crystal-scientific.com/xtal_orientation.html http://www.crystal-scientific.com/xtal_orientation.html
- deleted 8y ago[deleted]
- nl 8y agoNote that the TSMC 7nm process is similar in feature size to Intel 10nm. https://en.m.wikipedia.org/wiki/7_nanometer#7_nm_process_nodes https://en.m.wikipedia.org/wiki/7_nanometer#7_nm_process_nod...
- craftyguy 8y agoStrange that there's no citation for that claim.. do you have one?
- nl 8y agoHere’s a comparison of the GF 7nm and Intel 10nm. It’s the same for TSMC afaik https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge.html https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-...
- developer12 8y agoBoth Transistor Gate Pitch (nm) and Interconnect pitch (nm) are same or smaller for Intel's 10nm process compared to TSMC. https://en.wikipedia.org/wiki/10_nanometer https://en.wikipedia.org/wiki/10_nanometer
- sambull 8y agoLooks like Intel isn't having much luck there.
- ChuckMcM 8y agoFun stuff. I've got a key chain with an 80186 die, and a couple of the binders from Microprocessor Forum when they had dies on the cover. The features on those chips are "huge" compared to these things. I suspect a die using one of these processes that was big enough (say 100 sq mm) would just look like a mirror with chromatic interference lines running across it. This announcement also bookends nicely with the first home made IC one (https://hackaday.com/2018/04/24/first-lithographically-produced-home-made-ic-announced/ https://hackaday.com/2018/04/24/first-lithographically-produ...)
- opencl 8y agoICs have just looked like mirrors for a while now. See this shot of a 14nm Vega die on the left and 28nm Fury die on the right: https://www.techpowerup.com/reviews/AMD/Radeon_RX_Vega_Preview/images/rx-vega-die.jpg https://www.techpowerup.com/reviews/AMD/Radeon_RX_Vega_Previ...
- loser777 8y agoI think you linked to a flip chip---you would expect a mirror finish from the bulk silicon side.
- opencl 8y agoAh yes you're right of course. Has there been anything in the past few years made on modern processes with the die actually visible? Desktop/laptop CPUs and GPUs have all been flip chip for at least the past decade, mobile SoCs are package on package, most other stuff is encased in plastic.
- pantalaimon 8y agoder8auer did flip the Zen dies in the Threadripper over and ground them down to look what's inside. The video gives a good impression of the dimensions of the die and the structures inside. https://youtu.be/N-uKQ6RfUdk https://youtu.be/N-uKQ6RfUdk
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- bitL 8y agoI assume the production is already sold out for the next year for Bitcoin/Ethereum miner ASICs... I am wondering for how long will we be stuck with 7mm/10mm (Intel) tech; maybe we will see the last silicon-based improvements in CPUs & GPUs for the next two decades...
- ttul 8y agoDeep into science fiction here with EUV...
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- hardwaresofton 8y agoSo one of the most important questions when producing >10nm process is yield. In the article I can't really find yield numbers, and the only thing they mention is the SRAM chips getting "consistent double digits" -- so pessimistically consistently 10% yield. That's not "good" yield. Also, IIRC SRAMs are just about the simplest blocks you can make, which means they're the simplest lithography wise. Simple blocks to make, so they're usually good candidates for exploration of new process... 7nm is hard (I've said in a previous post, but you're just fighting physics at that point, nevermind all the issues you start facing with crosstalk/etc), color me skeptical that they've really nailed down a "volume" process for doing it just yet.
- calchris42 8y agoYields will suffer with current DUV process which must be multiple, multiple patterning. The mentioned switch to EUV reduces multiple patterning and should improve yield. But EUV has had its own challenges.
- awalton 8y ago> I can't really find yield numbers This is not surprising - this is trade secret information as it directly translates to profit margin for the process. AFAIK nobody publishes process yield information other than vague handwavy percentages. You should also expect percent yields of most processes these days to be pretty poor (numerically): each step brings its percent breakage along, so at 100+ steps for these current processes, you're losing a significant fraction of chips. (Even if all of your steps yield 99%, you're down to 36.6% yield after 100 steps, so it's really important to reduce the number of steps as well as their complexity.) For a process to be profitable it doesn't need to have a perfect, or even "good" yield though (and so-called "perfect wafers" have been vanishingly rare since about the 14nm process step). I've read documentation about very old processes with yields of 60% that were considered "good" at the time, so 10% might not be a terrible overall yield at this process node (e.g. if we take our 36.6% yield example above, 10% total yield would be of 27% of theoretical - certainly room for improvement, but better than many pharmaceutical processes). This underlines the importance for the switch to EUV - a dozen or more DUV multi-patterning steps can be dropped down to a single EUV step, which eliminates losses along those multi-patterning steps.
- fredch 8y agoWake me up when EUV's here...
- ekr 8y agoThis makes me hope that maybe all those chipmakers will finally move on from that extremely long-lived 28nm node. It has been heavily used since 2011-2012 and even companies like Qualcomm have been using it as recently as last year in the lower-end range of products. Companies like Allwinner, Rockchip, Amlogic have yet to release a single chip on newer nodes. What this means is that the 28nm node has been the cheapest now for 7 years running. Usually, when new nodes came up, the cost per transistor initially was lower, while the yields are slowly improving. But after ~1-2 years, the new node was always more cost-effective then older nodes, per-transistor. This wasn't the case with the 28nm, which stuck around for 7 whole years, and still seems to be the most cost-effective. But surely, now with 7nm available that won't be the case for much longer. Good riddance.
- phkahler 8y ago28nm will be around for a long time. There are SoCs up at 130 or 180nm still because for what they need those are the cheapest way to go. 28 is as far as you go with planar transistors and single (or is it double?) patterning. The 20-22 node is not popular because it kinda sucks for both planar and FinFET designs. I think 14-16 will be around for a long time too because of the increased complexity of going lower. While the end of scaling is a bummer, it will be nice to have the industry settle on a few common nodes that are mature and very well understood.
- nickik 8y agoGreat. I hope Esperanto Technology can come out with their RISC-V chip soon.
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