Ahh I forgot about zero instruction set computing. Maybe CISC should just stand for Compressed Instruction Stream Computing because on today's chips that's exac

Ahh I forgot about zero instruction set computing. Maybe CISC should just stand for Compressed Instruction Stream Computing because on today's chips that's exactly what it is. Cache hit-rates being similar may just show that the ad-hoc evolved compression codecs represented by CISC instruction sets are sub-optimal, hence my point about what might happen if we intentionally designed a CPU with on-board compression codec support for the instruction stream.