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Speaking of Moores law being dead this time, check out this old article from 2012 predicting we would be at 7nm Intel chips with 5nm on the way: http://www.toms

Speaking of Moores law being dead this time, check out this old article from 2012 predicting we would be at 7nm Intel chips with 5nm on the way: http://www.tomshardware.com/news/intel-cpu-processor-5nm,17578.html http://www.tomshardware.com/news/intel-cpu-processor-5nm,175... Intel is still trying to figure out 10nm because it is rumored that there are material science problems that are causing yield issues. Remember the 1960s when rapid gains in space tech made everyone think we'd be travelling around the solar system by 2000? The tech hit a plateau and stopped. Maybe we're in that situation with chip technology...

ribasushi 9y ago
An amazing 2014 talk[1]/article[2] by @idlewords explores exactly this premise. [1] https://www.youtube.com/watch?v=nwhZ3KEqUlw https://www.youtube.com/watch?v=nwhZ3KEqUlw [2] http://idlewords.com/talks/web_design_first_100_years.htm http://idlewords.com/talks/web_design_first_100_years.htm
duncan_bayne 9y ago
I thought it was more that the money dried up, and the nuclear test ban prohibited testing of the sorts of nuclear rockets that were being prototyped at the time.
- orbital-decay 9y ago
  It's the same with semiconductors though, the barrier is mostly economical.
  - donquichotte 9y ago
    Is it? I was under the impression that we are hitting physical barriers, like transistor size getting closer and closer to Silicon atom size.
    - orbital-decay 9y ago
      It's still technically possible to make chips with smaller nodes than the current mainstream processes allow, although this is uneconomical due to low yields and extremely thin margins.
  - Dylan16807 9y ago
    Has the budget for semiconductor research ever decreased? It's a tautology that we could be spending more money on it, but we are deeply investing in this field in a way that we stopped doing with space.
  - duncan_bayne 9y ago
    Right, so "Moore's law is dead" really scoped to "... affordable, conventional materials and designs that we've almost finished wringing every scrap of ROI out of". (That's not meant to be pejorative. Just saying I understand why companies would be loathe to ditch proven tooling w/ a lot of sunk costs).
pi-squared 9y ago
> Remember the 1960s when rapid gains in space tech made everyone think we'd be travelling around the solar system by 2000? I think space tech is a different beast economically - the intensive had been more to compete for global dominance in the 1960s and not so much demand (from the general public) to travel in space. I believe there is a bigger intensive to have faster processors now but we might be hitting physical/engineering limitations so we go distributed.
mcv 9y ago
Isn't nanometer scale also getting to the point that you're dealing with individual atoms? There is undoubtedly a point where you can't progress any further, and it seems reasonable that progress gets a lot harder as you approach that point.
- T-A 9y ago
  Atoms in a silicon crystal are about 0.54 nm apart, so we are not quite there yet.
  - dr_zoidberg 9y ago
    So you're saying a 10nm structure is about ~20 atoms long? So basically proving parents point...
    - T-A 9y ago
      No, saying that we are still an order of magnitude away from dealing with individual atoms. The current slowdown is more about light than about atoms; the move to EUV lithography [1] has proved to be very challenging [2]. [1] https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph... [2] https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturing https://spectrum.ieee.org/semiconductors/nanotechnology/euv-...
- Tuna-Fish 9y ago
  In the biz people already measure some widths as "monolayers", which refers to a single layer of atoms. Some process features have error margins of less than a monolayer -- that is, a dieletric needs to be 4 monolayers thick, and if it only has 3, the device is going to short, and if it has 5, the device will not work.
  - jjoonathan 9y ago
    What kind of CVD/PVD process do you use to achieve those kinds of tolerances? Or is the trick to use protect/deprotect steps like in conventional chemistry?
Nanite 9y ago
That and dark silicon: https://en.wikipedia.org/wiki/Dark_silicon https://en.wikipedia.org/wiki/Dark_silicon Running a modern CPU with an acceptable TDP, means only so much of the transistors can be utilized simultaneously .
slx26 9y ago
Anyway, around 5nm you start to have quantum tunneling effects. Current technology can't be scaled down much further. You can keep optimizing things, but you are still near the technology limits and increasing complexity.
- Tuna-Fish 9y ago
  Even though the numbers in process node names keep going down, this no longer directly corresponds to line widths. For example, the largest difference between TSMC 20nm and 16nm is that the way the transistor is built was completely changed. There are a couple of transitions like this left that buy real performance and density, even if the actual line widths stay as they are, so there likely will be a "3nm" process node. After that, who knows.
  - slx26 9y ago
    Agree it might be possible, but still, my point is that gains become smaller and smaller, more and more complex, and you still don't end up with transistors an order of magnitude smaller.
hardwaresofton 9y ago
Just want to let you know, as a person that worked at intel at one point -- 10nm is already plenty hard. @ 10nm and below, engineers/designers at intel (and a bunch of smaller more agile companies intel works with) are at this point just fighting physics as we know it at this point. There are promising technologies coming about, but since they're so different the amount of time it takes to perfect the process is super unforgiving, and intel is trying to navigate all that while putting out products that actually appeal to customers in different markets, planning them out at least a year in advance despite not having any idea what the market will look like in a year. Moore's law is super dead. If any company were to manage to keep up it would be nothing short of a miraculous revival.
atomicnumber1 9y ago
Why do we have to go below 10nm at all? We'll have hard physics limitations. Can't we improve on other frontiers? Say more cache?, better design ? More cores? Etc. I don't know.
- zanny 9y ago
  Making features smaller is far and away the most cost efficient way to make processors faster. It is also relevant to remember fan size and processor design are at least two independent divisions in the same company (Intel, Samsung) and are often two separate companies (AMD, TSMC). Its not like the chip makers arent investing engineers in design.
  - atomicnumber1 9y ago
    I see. I wonder what there strategy would be like? To double the efforts in reducing fab size or in other factors.
- ghettoimp 9y ago
  We can of course do both, and there is a lot of work on improving the designs. But scaling down the transistor size is generally a wonderful thing: smaller transistors use less power, produce less heat, and you can fit way more of them in the same area (which enables things like larger caches, etc.)
  - atomicnumber1 9y ago
    ok so I see that reducing fab size gives lot of benefits and they have steadily done so for past couple of decades. In doing so maybe they overlooked on design or other factors? And now that we've hit the wall on fab sizes (purportedly), maybe they can double their efforts on other factors.
    - T-A 9y ago
      That reminds me of this talk from 2013: https://www.youtube.com/watch?v=JpgV6rCn5-g https://www.youtube.com/watch?v=JpgV6rCn5-g The gist of it, as I remember it, is that radical design ideas were a bad investment while Moore's law ruled, because they were likely to be outperformed by simply shrinking the standard architecture; after Moore, design gains in importance, but don't expect anything like the performance improvements of the past half century.
fallingfrog 9y ago
How are GPUs still apparently increasing their power exponentially without using more power? It looks like the best 10 series NVIDIA GPU has about twice the power of the best 9 series, about 2 years earlier, which lines up with Moore's Law pretty closely. How are they doing it? Maybe they were actually lagging Intel- looks like the 9 series was a 28nm process, and the 10 series is a 14 or 16nm process.
- coryfklein 9y ago
  I can't answer authoritatively, but I would speculate it has to do with the highly parallel nature of GPUs.
- Retric 9y ago
  Yea, GPU's are a few nodes behind which means they will take longer to hit the same wall. Even the GTX 1080 Ti just hit 16nm. Compare a 95 W (22nm) i7 2600k from January 2011 vs 65 W (14nm) Core i7-8706G from February 2018, that's over 7 years of progress for 30% lower power consumption and a fair speed boost. That's what GPU's are facing starting now, though they can directly trade lower power consumption for more speed as they are embarrassingly parallel.
deepnotderp 9y ago
To be more specific: the rumor is that integration of cobalt is the issue.
- tpurves 9y ago
  Can youbelaborate? What does cobalt have to do with the current nodes? And killer as in good or killer as in bad?
  - deepnotderp 9y ago
    Sure, so Intel is using cobalt at low dimension interconnects (e.g. M0-3) because cobalt has lower resistance than copper at low dimensions due to electron mean free path issues. The rumor is that integration of the cobalt material is what's causing yield issues at Intel for 10nm.

ribasushi 9y ago

An amazing 2014 talk[1]/article[2] by @idlewords explores exactly this premise. [1] https://www.youtube.com/watch?v=nwhZ3KEqUlw https://www.youtube.com/watch?v=nwhZ3KEqUlw [2] http://idlewords.com/talks/web_design_first_100_years.htm http://idlewords.com/talks/web_design_first_100_years.htm

duncan_bayne 9y ago

I thought it was more that the money dried up, and the nuclear test ban prohibited testing of the sorts of nuclear rockets that were being prototyped at the time.

orbital-decay 9y ago
It's the same with semiconductors though, the barrier is mostly economical.
- donquichotte 9y ago
  Is it? I was under the impression that we are hitting physical barriers, like transistor size getting closer and closer to Silicon atom size.
  - orbital-decay 9y ago
    It's still technically possible to make chips with smaller nodes than the current mainstream processes allow, although this is uneconomical due to low yields and extremely thin margins.
- Dylan16807 9y ago
  Has the budget for semiconductor research ever decreased? It's a tautology that we could be spending more money on it, but we are deeply investing in this field in a way that we stopped doing with space.
- duncan_bayne 9y ago
  Right, so "Moore's law is dead" really scoped to "... affordable, conventional materials and designs that we've almost finished wringing every scrap of ROI out of". (That's not meant to be pejorative. Just saying I understand why companies would be loathe to ditch proven tooling w/ a lot of sunk costs).

pi-squared 9y ago

> Remember the 1960s when rapid gains in space tech made everyone think we'd be travelling around the solar system by 2000? I think space tech is a different beast economically - the intensive had been more to compete for global dominance in the 1960s and not so much demand (from the general public) to travel in space. I believe there is a bigger intensive to have faster processors now but we might be hitting physical/engineering limitations so we go distributed.

mcv 9y ago

Isn't nanometer scale also getting to the point that you're dealing with individual atoms? There is undoubtedly a point where you can't progress any further, and it seems reasonable that progress gets a lot harder as you approach that point.

T-A 9y ago
Atoms in a silicon crystal are about 0.54 nm apart, so we are not quite there yet.
- dr_zoidberg 9y ago
  So you're saying a 10nm structure is about ~20 atoms long? So basically proving parents point...
  - T-A 9y ago
    No, saying that we are still an order of magnitude away from dealing with individual atoms. The current slowdown is more about light than about atoms; the move to EUV lithography [1] has proved to be very challenging [2]. [1] https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph... [2] https://spectrum.ieee.org/semiconductors/nanotechnology/euv-lithography-finally-ready-for-chip-manufacturing https://spectrum.ieee.org/semiconductors/nanotechnology/euv-...
Tuna-Fish 9y ago
In the biz people already measure some widths as "monolayers", which refers to a single layer of atoms. Some process features have error margins of less than a monolayer -- that is, a dieletric needs to be 4 monolayers thick, and if it only has 3, the device is going to short, and if it has 5, the device will not work.
- jjoonathan 9y ago
  What kind of CVD/PVD process do you use to achieve those kinds of tolerances? Or is the trick to use protect/deprotect steps like in conventional chemistry?

Nanite 9y ago

That and dark silicon: https://en.wikipedia.org/wiki/Dark_silicon https://en.wikipedia.org/wiki/Dark_silicon Running a modern CPU with an acceptable TDP, means only so much of the transistors can be utilized simultaneously .

slx26 9y ago

Anyway, around 5nm you start to have quantum tunneling effects. Current technology can't be scaled down much further. You can keep optimizing things, but you are still near the technology limits and increasing complexity.

Tuna-Fish 9y ago
Even though the numbers in process node names keep going down, this no longer directly corresponds to line widths. For example, the largest difference between TSMC 20nm and 16nm is that the way the transistor is built was completely changed. There are a couple of transitions like this left that buy real performance and density, even if the actual line widths stay as they are, so there likely will be a "3nm" process node. After that, who knows.
- slx26 9y ago
  Agree it might be possible, but still, my point is that gains become smaller and smaller, more and more complex, and you still don't end up with transistors an order of magnitude smaller.

hardwaresofton 9y ago

Just want to let you know, as a person that worked at intel at one point -- 10nm is already plenty hard. @ 10nm and below, engineers/designers at intel (and a bunch of smaller more agile companies intel works with) are at this point just fighting physics as we know it at this point. There are promising technologies coming about, but since they're so different the amount of time it takes to perfect the process is super unforgiving, and intel is trying to navigate all that while putting out products that actually appeal to customers in different markets, planning them out at least a year in advance despite not having any idea what the market will look like in a year. Moore's law is super dead. If any company were to manage to keep up it would be nothing short of a miraculous revival.

atomicnumber1 9y ago

Why do we have to go below 10nm at all? We'll have hard physics limitations. Can't we improve on other frontiers? Say more cache?, better design ? More cores? Etc. I don't know.

zanny 9y ago
Making features smaller is far and away the most cost efficient way to make processors faster. It is also relevant to remember fan size and processor design are at least two independent divisions in the same company (Intel, Samsung) and are often two separate companies (AMD, TSMC). Its not like the chip makers arent investing engineers in design.
- atomicnumber1 9y ago
  I see. I wonder what there strategy would be like? To double the efforts in reducing fab size or in other factors.
ghettoimp 9y ago
We can of course do both, and there is a lot of work on improving the designs. But scaling down the transistor size is generally a wonderful thing: smaller transistors use less power, produce less heat, and you can fit way more of them in the same area (which enables things like larger caches, etc.)
- atomicnumber1 9y ago
  ok so I see that reducing fab size gives lot of benefits and they have steadily done so for past couple of decades. In doing so maybe they overlooked on design or other factors? And now that we've hit the wall on fab sizes (purportedly), maybe they can double their efforts on other factors.
  - T-A 9y ago
    That reminds me of this talk from 2013: https://www.youtube.com/watch?v=JpgV6rCn5-g https://www.youtube.com/watch?v=JpgV6rCn5-g The gist of it, as I remember it, is that radical design ideas were a bad investment while Moore's law ruled, because they were likely to be outperformed by simply shrinking the standard architecture; after Moore, design gains in importance, but don't expect anything like the performance improvements of the past half century.

fallingfrog 9y ago

How are GPUs still apparently increasing their power exponentially without using more power? It looks like the best 10 series NVIDIA GPU has about twice the power of the best 9 series, about 2 years earlier, which lines up with Moore's Law pretty closely. How are they doing it? Maybe they were actually lagging Intel- looks like the 9 series was a 28nm process, and the 10 series is a 14 or 16nm process.

coryfklein 9y ago
I can't answer authoritatively, but I would speculate it has to do with the highly parallel nature of GPUs.
Retric 9y ago
Yea, GPU's are a few nodes behind which means they will take longer to hit the same wall. Even the GTX 1080 Ti just hit 16nm. Compare a 95 W (22nm) i7 2600k from January 2011 vs 65 W (14nm) Core i7-8706G from February 2018, that's over 7 years of progress for 30% lower power consumption and a fair speed boost. That's what GPU's are facing starting now, though they can directly trade lower power consumption for more speed as they are embarrassingly parallel.

deepnotderp 9y ago

To be more specific: the rumor is that integration of cobalt is the issue.

tpurves 9y ago
Can youbelaborate? What does cobalt have to do with the current nodes? And killer as in good or killer as in bad?
- deepnotderp 9y ago
  Sure, so Intel is using cobalt at low dimension interconnects (e.g. M0-3) because cobalt has lower resistance than copper at low dimensions due to electron mean free path issues. The rumor is that integration of the cobalt material is what's causing yield issues at Intel for 10nm.