4 ms·
Do you think they actually mean 900Gb/s (Gbit) here? 18 ports of todays ~50Gb/s serdes would give 900Gb/s. And that'd be twice the bandwidth of their Nvlink 2.0
by kingosticks 9y ago
Do you think they actually mean 900Gb/s (Gbit) here? 18 ports of todays ~50Gb/s serdes would give 900Gb/s. And that'd be twice the bandwidth of their Nvlink 2.0 stuff (~25Gb/s), which would seem a reasonable evolution.
Edit: Turns out that a single Nvlink 3.0 port is 8-bits wide and since 144 50Gb/s serdes on a (big) chip is perfectly doable - 900GB/s must be correct.
- ethbro 9y agoThe article notes it's a 2B transistor switch chip... which boggles the mind.
- imtringued 9y agoPCIe 3.0 x16 already is capable of more than 100gbps per port. 900gbits total bandwidth for 18 NVLink ports would be abysmally slow.