10 ms·

Implementing FizzBuzz on an FPGA

261 points by jf 9y ago

Cyph0n 9y ago
Great article! I've also been learning Verilog -- albeit in an academic setting -- and it has been an interesting experience. I discovered that you can do surprisingly complex things in Verilog (at least, from a digital logic point of view) using less code than I initially expected!
- InitialLastName 9y ago
  I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.
  - Cyph0n 9y ago
    The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states
    - eebynight 9y ago
      Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.
      - q3k 9y ago
        Depends on where you're located. Counter anecdata: I've seen much more EE jobs asking for Verilog than VHDL :).
      - dzamlo 9y ago
        From what I read, this is very different between the US and Europe.
      - TomVDB 9y ago
        VHDL is popular in Europe and the US East Coast. Verilog is king on the West Coast. An an EE who was schooled in VHDL, gave VHDL classes to new hires and was conditioned to look down on Verilog: after moving from Europe to the East Coast and then the West Coast, I eventually saw the error of my ways and I'm very happy to not have to deal with VHDL anymore. And for the open source crowd: there is a much large body of decent quality open source Verilog tools than there is for VHDL. So as a hobbyist, it's really a nobrainer.
        monocasa 9y ago
        I always got more of a VHDL for FPGAs and Verilog for chips kind of vibe. Not that there's anything intrinsic in those languages, just the kinds of industries that ship FPGAs seem to gravitate to a DoD specified language. And can you elaborate on what you like about Verilog?
      - JoachimS 9y ago
        That is very strange. Verilog and SystemVerilog totally dominates VHDL across the globe in terms of market share. Including Europe. Esp if you are designing ASICs, but also for FPGAs. If you are desinging ASICs and use VHDL you will quite likely end up having mixed language RTL design. And after synthesis the netlist will be in Verilog. So any co-simulation between RTL and netlist must support both languages. Which costs extra in licenses. Other reasons for choosing Verilog is that the tool developers (being mainly in the US) knows Verilog best. If you look at the adaption rate of new language features, Verilog (SystemVerilog) gets much more attention. VHDL is for some reason considered a good school language. I don't see the point of it. It's a bit like teaching the ISO stack. The industry has chosen another stack, the pedagogical value if ISO vs TCP/IP is slim to none. The same can (imho) be said for VHDL.
    - TomVDB 9y ago
      * Never use asynchronous resets [on FPGAs] It makes no difference for most FPGAs. Most have dedicated resources dedicated to resets and consume equal resources for async and sync resets. For ASIC, sync resets these days are considered safer against glitches because they only have an impact during a rising edge of the clock instead of all the time. But it's not something to be super religious about.
      - Cyph0n 9y ago
        From my understanding, many FPGAs do not have a dedicated reset distribution network. Instead, P&R consumes a ton of resources to propagate resets across the chip. My information could be out of date though!
    - JoachimS 9y ago
      Sometimes if-else-chaining is what you need. But if you are doing one of n-select, a switch is what you should use. If you are using Verilog 2001 or later, you can use always @* to implicitly declare all variables a combinational process depends on. It used to be a huge source of latches. I would also highly advice against mixing blocking (i.e a = x) and non-blocking (i.e. a <= x) assignments in one process. I usually write a single clocked process with all registers and then only have a few extra combinational processes for the logic. I also recommend separating data path logic (the processing you do) with the control path (the FSM that keep track of what is happening inside your machine). Never assume values or states is really good. I usually assign default states at the top of processes. Then for other state you only have to define that. It is really helpful in FSMs. Not claiming to having a great coding style, but if you want some examples on RTL code and testbenches here are my cores for AES, SHA256 and many others: https://github.com/secworks https://github.com/secworks
      - Cyph0n 9y ago
        Thanks for the pointers! Actually, the first thing our professor taught us is when exactly to use blocking and non-blocking and that they should never be mixed. By the way, I ran across some of your code on GH about a year back and have been following you ever since. Nice coincidence haha :)
lnsru 9y ago
Amazing project to learn how FPGAs work. Not overkill with some high speed interfaces, but touches all problems: no easy division by 3 and 5, counters everywhere, no copy/paste solutions, no libraries with helpful functions. Though Xilinx ISE is obsolete, Vivado is the current tool.
- kens 9y ago
  Unfortunately Vivado doesn't support the Spartan 6 chip used by the Mojo board, just Spartan 7 and later.
- Posibyte 9y ago
  As kens said, and to expand, Xilinx's Vivado doesn't support the Spartan 6, however they _do_ still fully support the Spartan 6 and continue to produce new chips. To support this, they've released a Virtualbox compatible image which runs Oracle Linux with ISE configured specifically to program Spartan 6 FPGAs.[1] [1]: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html https://www.xilinx.com/support/download/index.html/content/x...
- jdswain 9y ago
  And the QFP Spartan 6 is the most powerful Xilinx FPGA that is hand solderable. Maybe not a concern if you are using an existing board or have a reflow oven, but for me that is a good reason not to go up to Spartan 7 or newer.
mrguyorama 9y ago
The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy
- leggomylibro 9y ago
  I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor. But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up. It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, though!
  - gh02t 9y ago
    > But it's hard to find and get started with a good open source toolchain That's because there aren't any. The one you have happens to be the exception - it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the realm of large, heavily proprietary build environments.
    - MisterTea 9y ago
      > That's because there aren't any. Incorrect. See: http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
      - gh02t 9y ago
        I meant to explicitly say that the Lattice iCE40 is the one exception thanks to a heroic volunteer effort. I edited a bit to make that clearer.
    - Crisco 9y ago
      I was complaining about that the other day. I'm a pretty big fan and proponent of the Libre software movement and have recently decided I want to help with an open hardware movement because it is almost impossible to do any serious work with FPGAs using only FOSS. Does anyone know of any good places to start and help?
vvanders 9y ago
> While this may look like code in a normal programming language, it operates entirely differently. So happy to see this called out up-front. One of the hardest things with FPGAs as a developer is understanding that you're reconfiguring hardware instead of a series of serial asm/opcodes. They look superficially the same but have very different requirements and constraints under the hood.
- katastic 9y ago
  Think of it more like SQL, where you're describing a model, then a series of steps.
  - nickpsecurity 9y ago
    Maybe more like dataflow or flow-based programming. Let them play with those a while. Then, make the black boxes FSM's with serious constraints about size or execution time. They'll start getting the idea. Messing with a synchronous or time-oriented language might help, too, in terms of a metaphor for clocks.
- pjmlp 9y ago
  It depends very much where we as developers come from. My CS degree had quite a few sections of electronic lectures. In fact, one way I always looked at function composition in FP languages was to think of them as digital circuit modules.
  - vvanders 9y ago
    That's still an impartial model because each layer of abstraction can introduce path delay and resource usage. Functional programming doesn't encapsulate interfacing across different clock domains or one hot vs binary state representation. Trying to bring those abstraction models to HDL you'll find a significant impedance mismatch.
    - pjmlp 9y ago
      True, still it is easier than trying to think in imperative programming when doing FPGA programming. There are quite a few books using LP and FP for modelling of digital circuits. You can also introduce signal propagation modeling on them.
cesarb 9y ago
Would it have been better to use a ring counter instead of an adder for the modulo 3, modulo 5, and state counters?
- JoachimS 9y ago
  Yes, parallel counters would be a simpler solution.
- 8note 9y ago
  significantly more efficient and fpga-like
TomVDB 9y ago
For those looking for cheap FPGA boards, I highly recommend looking for something that is based on the Lattice ICE40. The cheapest board you can find is probably the $9 Upduino, though trickier to get going. (Complete lack of documentation.) But there are tons of hobby boards in existence. The best part is Project IceStorm, a fully open source tool flow, from synthesis to bitstream. While not the best in terms of optimization, it's killer feature is that it's blazing fast. You can get small design synthesized and converted to a place-and-routed bitstream in under a minute.
- katastic 9y ago
  My problem (years ago) was that with Lattice, there just aren't as many tutorials/easy-EDA and they kind of expect you to know what you're doing. So if you've never taken a class on FPGA's and learned how netlists work, et al, Lattice may be a harder time. I ended up buying a cheap Altera afterward just to learn.
  - nmz787 9y ago
    I think that's solved now though, at least for a few ICs and toolchains, via things like MyHDL and/or rhea (tldr; Python wrappers) and websites like fpga4fun.com
  - bri3d 9y ago
    I entirely see where you're coming from, and this has completely changed in the last 2-3 years. SiliconBlue/Lattice used to be a niche-market low-power also ran in the FPGA world. Documentation was sparse and most examples from academia targeted Altera or Xilinx parts. The open-source toolchain flipped this and allowed Lattice FPGAs to become the tool of choice for beginners and small-application hobbyists. There's now a tremendous wealth of resource available around getting started with Lattice FPGAs. And as the cherry on top, you don't have to wrangle the gigantic Vivado/Quartus/ISE suites to do so.
- wepple 9y ago
  I’d highly recommend the IceStick for $21 - not only do you get an FPGA but it has an ft2232, so you have a serial adapter and basic JTAG adapter for free! I’d keep one on my keychain if I could (it’s a tad too large).
deleted 9y ago
[deleted]
sguav 9y ago
I am pleasantly surprised by this reading! I have been trained as an EE to consider FPGA design in the hardware skills domain, and indeed I would say that this writeup ignores the less friendly parts of FPGA development (timing closure, clock domain crossing and more...). Nevertheless, I think it is a good introduction for software developers to start thinking like "hardware description". Good work!

261 points by jf 9y ago

Great article! I've also been learning Verilog -- albeit in an academic setting -- and it has been an interesting experience. I discovered that you can do surprisingly complex things in Verilog (at least, from a digital logic point of view) using less code than I initially expected!

InitialLastName 9y ago
I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.
- Cyph0n 9y ago
  The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states
  - eebynight 9y ago
    Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.
    - q3k 9y ago
      Depends on where you're located. Counter anecdata: I've seen much more EE jobs asking for Verilog than VHDL :).
    - dzamlo 9y ago
      From what I read, this is very different between the US and Europe.
    - TomVDB 9y ago
      VHDL is popular in Europe and the US East Coast. Verilog is king on the West Coast. An an EE who was schooled in VHDL, gave VHDL classes to new hires and was conditioned to look down on Verilog: after moving from Europe to the East Coast and then the West Coast, I eventually saw the error of my ways and I'm very happy to not have to deal with VHDL anymore. And for the open source crowd: there is a much large body of decent quality open source Verilog tools than there is for VHDL. So as a hobbyist, it's really a nobrainer.
      - monocasa 9y ago
        I always got more of a VHDL for FPGAs and Verilog for chips kind of vibe. Not that there's anything intrinsic in those languages, just the kinds of industries that ship FPGAs seem to gravitate to a DoD specified language. And can you elaborate on what you like about Verilog?
    - JoachimS 9y ago
      That is very strange. Verilog and SystemVerilog totally dominates VHDL across the globe in terms of market share. Including Europe. Esp if you are designing ASICs, but also for FPGAs. If you are desinging ASICs and use VHDL you will quite likely end up having mixed language RTL design. And after synthesis the netlist will be in Verilog. So any co-simulation between RTL and netlist must support both languages. Which costs extra in licenses. Other reasons for choosing Verilog is that the tool developers (being mainly in the US) knows Verilog best. If you look at the adaption rate of new language features, Verilog (SystemVerilog) gets much more attention. VHDL is for some reason considered a good school language. I don't see the point of it. It's a bit like teaching the ISO stack. The industry has chosen another stack, the pedagogical value if ISO vs TCP/IP is slim to none. The same can (imho) be said for VHDL.
  - TomVDB 9y ago
    * Never use asynchronous resets [on FPGAs] It makes no difference for most FPGAs. Most have dedicated resources dedicated to resets and consume equal resources for async and sync resets. For ASIC, sync resets these days are considered safer against glitches because they only have an impact during a rising edge of the clock instead of all the time. But it's not something to be super religious about.
    - Cyph0n 9y ago
      From my understanding, many FPGAs do not have a dedicated reset distribution network. Instead, P&R consumes a ton of resources to propagate resets across the chip. My information could be out of date though!
  - JoachimS 9y ago
    Sometimes if-else-chaining is what you need. But if you are doing one of n-select, a switch is what you should use. If you are using Verilog 2001 or later, you can use always @* to implicitly declare all variables a combinational process depends on. It used to be a huge source of latches. I would also highly advice against mixing blocking (i.e a = x) and non-blocking (i.e. a <= x) assignments in one process. I usually write a single clocked process with all registers and then only have a few extra combinational processes for the logic. I also recommend separating data path logic (the processing you do) with the control path (the FSM that keep track of what is happening inside your machine). Never assume values or states is really good. I usually assign default states at the top of processes. Then for other state you only have to define that. It is really helpful in FSMs. Not claiming to having a great coding style, but if you want some examples on RTL code and testbenches here are my cores for AES, SHA256 and many others: https://github.com/secworks https://github.com/secworks
    - Cyph0n 9y ago
      Thanks for the pointers! Actually, the first thing our professor taught us is when exactly to use blocking and non-blocking and that they should never be mixed. By the way, I ran across some of your code on GH about a year back and have been following you ever since. Nice coincidence haha :)

lnsru 9y ago

Amazing project to learn how FPGAs work. Not overkill with some high speed interfaces, but touches all problems: no easy division by 3 and 5, counters everywhere, no copy/paste solutions, no libraries with helpful functions. Though Xilinx ISE is obsolete, Vivado is the current tool.

kens 9y ago
Unfortunately Vivado doesn't support the Spartan 6 chip used by the Mojo board, just Spartan 7 and later.
Posibyte 9y ago
As kens said, and to expand, Xilinx's Vivado doesn't support the Spartan 6, however they _do_ still fully support the Spartan 6 and continue to produce new chips. To support this, they've released a Virtualbox compatible image which runs Oracle Linux with ISE configured specifically to program Spartan 6 FPGAs.[1] [1]: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html https://www.xilinx.com/support/download/index.html/content/x...
jdswain 9y ago
And the QFP Spartan 6 is the most powerful Xilinx FPGA that is hand solderable. Maybe not a concern if you are using an existing board or have a reflow oven, but for me that is a good reason not to go up to Spartan 7 or newer.

mrguyorama 9y ago

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

leggomylibro 9y ago
I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor. But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up. It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, though!
- gh02t 9y ago
  > But it's hard to find and get started with a good open source toolchain That's because there aren't any. The one you have happens to be the exception - it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the realm of large, heavily proprietary build environments.
  - MisterTea 9y ago
    > That's because there aren't any. Incorrect. See: http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/
    - gh02t 9y ago
      I meant to explicitly say that the Lattice iCE40 is the one exception thanks to a heroic volunteer effort. I edited a bit to make that clearer.
  - Crisco 9y ago
    I was complaining about that the other day. I'm a pretty big fan and proponent of the Libre software movement and have recently decided I want to help with an open hardware movement because it is almost impossible to do any serious work with FPGAs using only FOSS. Does anyone know of any good places to start and help?

vvanders 9y ago

> While this may look like code in a normal programming language, it operates entirely differently. So happy to see this called out up-front. One of the hardest things with FPGAs as a developer is understanding that you're reconfiguring hardware instead of a series of serial asm/opcodes. They look superficially the same but have very different requirements and constraints under the hood.

katastic 9y ago
Think of it more like SQL, where you're describing a model, then a series of steps.
- nickpsecurity 9y ago
  Maybe more like dataflow or flow-based programming. Let them play with those a while. Then, make the black boxes FSM's with serious constraints about size or execution time. They'll start getting the idea. Messing with a synchronous or time-oriented language might help, too, in terms of a metaphor for clocks.
pjmlp 9y ago
It depends very much where we as developers come from. My CS degree had quite a few sections of electronic lectures. In fact, one way I always looked at function composition in FP languages was to think of them as digital circuit modules.
- vvanders 9y ago
  That's still an impartial model because each layer of abstraction can introduce path delay and resource usage. Functional programming doesn't encapsulate interfacing across different clock domains or one hot vs binary state representation. Trying to bring those abstraction models to HDL you'll find a significant impedance mismatch.
  - pjmlp 9y ago
    True, still it is easier than trying to think in imperative programming when doing FPGA programming. There are quite a few books using LP and FP for modelling of digital circuits. You can also introduce signal propagation modeling on them.

cesarb 9y ago

Would it have been better to use a ring counter instead of an adder for the modulo 3, modulo 5, and state counters?

JoachimS 9y ago
Yes, parallel counters would be a simpler solution.
8note 9y ago
significantly more efficient and fpga-like

TomVDB 9y ago

For those looking for cheap FPGA boards, I highly recommend looking for something that is based on the Lattice ICE40. The cheapest board you can find is probably the $9 Upduino, though trickier to get going. (Complete lack of documentation.) But there are tons of hobby boards in existence. The best part is Project IceStorm, a fully open source tool flow, from synthesis to bitstream. While not the best in terms of optimization, it's killer feature is that it's blazing fast. You can get small design synthesized and converted to a place-and-routed bitstream in under a minute.

katastic 9y ago
My problem (years ago) was that with Lattice, there just aren't as many tutorials/easy-EDA and they kind of expect you to know what you're doing. So if you've never taken a class on FPGA's and learned how netlists work, et al, Lattice may be a harder time. I ended up buying a cheap Altera afterward just to learn.
- nmz787 9y ago
  I think that's solved now though, at least for a few ICs and toolchains, via things like MyHDL and/or rhea (tldr; Python wrappers) and websites like fpga4fun.com
- bri3d 9y ago
  I entirely see where you're coming from, and this has completely changed in the last 2-3 years. SiliconBlue/Lattice used to be a niche-market low-power also ran in the FPGA world. Documentation was sparse and most examples from academia targeted Altera or Xilinx parts. The open-source toolchain flipped this and allowed Lattice FPGAs to become the tool of choice for beginners and small-application hobbyists. There's now a tremendous wealth of resource available around getting started with Lattice FPGAs. And as the cherry on top, you don't have to wrangle the gigantic Vivado/Quartus/ISE suites to do so.
wepple 9y ago
I’d highly recommend the IceStick for $21 - not only do you get an FPGA but it has an ft2232, so you have a serial adapter and basic JTAG adapter for free! I’d keep one on my keychain if I could (it’s a tad too large).

deleted 9y ago

[deleted]

sguav 9y ago

I am pleasantly surprised by this reading! I have been trained as an EE to consider FPGA design in the hardware skills domain, and indeed I would say that this writeup ignores the less friendly parts of FPGA development (timing closure, clock domain crossing and more...). Nevertheless, I think it is a good introduction for software developers to start thinking like "hardware description". Good work!