3 ms·

Reading the NXP thread, it is not yet clear that NXP considers this errata, only that it is something that is desirable to avoid. Does anyone have a link to th

• ChuckMcM 9y ago
  In that thread -- After reproducing the issue and performing some tests, it was found that the issue is because “LDREX” and “STREX” instructions overlooked LMEM cache. That means those instructions always access external memory directly, which leads to data inconsistency. There’s no SW configuration to make the cacheable data consistent with those atomic instructions, and design team will fix it in later CM4 integration. Its a bug. But they see a workaround so they aren't in a hurry to fix it apparently.
  • Gibbon1 9y ago
    That reminds me of an article about a similar problem with the xbox. Cache consistency is extremely brittle combine that with speculative execution and that means just having instructions that break cache consistency in memory is dangerous.
    • Dylan16807 9y ago
      Here you go: https://randomascii.wordpress.com/2018/01/07/finding-a-cpu-design-bug-in-the-xbox-360/ https://randomascii.wordpress.com/2018/01/07/finding-a-cpu-d... https://news.ycombinator.com/item?id=16094925 https://news.ycombinator.com/item?id=16094925