8 ms·
How to Design a New Chip on a Budget
- anfilt 9y agoI have thought about this. I have looked at several multi-wafer services for my own projects. Mainly some interesting analog designs mixed with digital. For instance http://cmp.imag.fr/ http://cmp.imag.fr/ has a 350nm process for only 650 euros per sq mm. However, that does exclude packaging costs which is quite steep for such a low number of devices.
- yzhou 9y agominimum 5.5mm^2 is required, so we are talking about 3575 euros here. Besides, it is very rare that you can get a production grade chip on the first try, bug happens all the time, you might need 2 or 3 or even more tries to get a working product.
- jacquesm 9y agoYou might, but there are plenty of examples of first Silicon working, the trick is to spend a lot of time on getting your simulations right.
- deleted 9y ago[deleted]
- srcmap 9y agoThe article mentions "Magic" as open source design tools. I was hired by UC Davis as Summer Intern to work on porting it from X10 to X11 in 1988. Very cools to see it still around and being used after 30 years!
- FPGAhacker 9y agoI believe the major disruption waiting to happen in chip design is open source tools, and the hardware languages. Frankly, the closed source tools are pretty awful from a user interface perspective. Under the hood, amazing things happen, but the tools are pretty awful to use. and the languages... ugh, the languages. Our big leap forward was SystemVerilog. It's a bastardization of three languages: of 80's c++, 80's Verilog, and an interesting constraint solver in a distinct dialect. We need (in my humble opinion): * Open source high performance discrete event simulator (language agnostic, use an intermediate representation like a source mapped netlist) * Said simulator, but distributed (multi core, process, data center) * An ecosystem that encourages language development (Said simulator could help) * An open source synthesis framework that can read the intermediate representation netlist. * GUIs that don't cause eye hemorrhaging and monitor punching.
- pjc50 9y agoHaving spent about a decade in a chip design software startup that was eventually bought by Cadence, I'll say: - you're absolutely right that the tools are horrible to use, and Verilog's time is up - existing chip design companies are extremely conservative and hate adopting anything new even from their own preferred vendor, because risk - a lot of the key knowledge is spread by apprenticeship and oral culture; analog IC engineers are another culture altogether
- phlipski 9y agoI spent over a decade doing circuit design and I can corroborate your points. Chip design is maddening! One of the most interesting differences between software and hardware engineering is how many blogs and writing on the web you can find about software. You can almost self teach a masters in CS through online blogs and various postings! The only writing you find online about hardware is either patent's or IEEE white-papers. There is still something magical when a new chip design comes back from the fab and boots up!
- adapteva 9y agoWorking on it... https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001117S0054/listing.html https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001117S0054/listing....
- kumarski 9y agohttp://efabless.com http://efabless.com does 180nm open source in the browser window and you get a chip in the package at 5K USD or less. Xfab is on the backend.
- schappim 9y agoThe TL;DR; of this article is: "...a simple ASIC (say one that is a few square millimeters in size, fabricated using the 250-nm technology node) might cost a few thousand bucks for a couple dozen samples."
- pjc50 9y agoThere's a lot of people quoting the price in this thread but very few coming forwards to say "yes, I've actually done this".
- Hasz 9y agoThe number of people with the experience, knowledge, cash, and who are not bound by NDA is very small.
- deepnotderp 9y agoLiterally everyone who has done this is bound by NDA. Every single foundry will make you sign one.
- anfilt 9y agoHaving signed the a couple of those NDAs. The foundries are mainly concerned about their standard cell library, and any information that may let a competitor understand the details of their lithographic process. Most engineers just use the cell library from foundry, but cell library does contain information about a foundry's process. A lot foundries will let you make chips without using their cell library. You some times have to make complete custom components in the analog world. (Be warned this a ton of work and is no easy under taking) However, even if you developed your own cell library for a particular foundry. It will still be tied by an NDA since it may leak information about how the foundry handles optical proximity correction and uses phase shifting (of light) for their process to increase resolution. Also how many layers it takes to implement something and how each of those layers have particular characteristics may reveal some of the chemistry and material science used to dope the silicon or create certain structure for their process. ~edit a few typos/omissions~
- anonymousDan 9y agoHow easy is it to take code written for an FPGA and transfer it to run on an ASIC (e.g. code written in Verilog). Are they so different it would need to be rewritten from scratch, or could it be done with the equivalent of a a recompile? Do people often use FPGAs as a stepping stone to a custom ASIC design? Would learning how to program FPGAs be of any use when it comes to designing ASICs? I'm interested in getting into FPGAs, but I can't help but worry they are a bit of a dead end as any sufficiently popular use case will eventually be replaced by an ASIC.
- FPGAhacker 9y agoFPGAs are definitely not a dead end. By virtue of being reconfigurable, they will never be obsolete as long as ASICs are a thing. Now, some whole new technology will come along eventually, supplanting present day ASICs and FPGAs... but until then... Program as a term means something different with chip design than it does with software. An analogy is that to program an FPGA is to paint a canvas. The source code in chip design is instructions for how the canvas should be painted. Another analogy would be to program an FPGA is to cook a meal. The source code is the recipe for the meal. But one doesn't run a recipe on a meal. These analogies break down because a painting and a meal is passive... it doesn't do anything by itself, or react to the outside world. So another analogy would be building a car. Here "programming" and "building" are the analogous terms. The instructions for the assembly line to construct the car is the source code. Once built, the car responds to stimulus (steering wheel, pedals) and does stuff. Same with the FPGA. It has inputs, it responds and does stuff. If you painted a picture of a CPU in your FPGA, it could run software. There is tremendous overlap in designing for an FPGA and an ASIC. Most ASICs start life as an FPGA simply to prototype an idea. The difference between an ASIC and an FPGA, at a high level from a design perspective, is the difference between writing with a pen vs a pencil. Learning to write is equally applicable. It's probably not helpful to think about right now, but an FPGA is actually an ASIC.
- deepnotderp 9y agoThe LUT based architecture is starting to run out of steam, I think a CGRA sort of architecture is the future, but programmable logic startups will likely fail, and there's approximately a zero percent chance that Xilinx or Altera would try anything that new.
- vegetablepotpie 9y agoQuestion, I read that fabs use specific, proprietary technology to produce ASICs and this technology is protected by NDAs and Trade Secrets. Some components require intimate process knowledge, which may never be open. Why wouldn't these companies have patented these technologies? Granted there isn't a lot of love for patents with software, but I think ASIC design is a case where the concept would be beneficial for the public. Although the fabs would have a monopoly on their process for a time, it would atleast be published so that open source tools could be made that take advantage of these processes.
- kijiki 9y agoProcess technology details go out of date quickly, so trade secrets/NDAs work well enough. Patents are more expensive and require explicit disclosure.
- analognoise 9y agoYou said it yourself: "Although the fabs would have a monopoly on their process for a time, it would atleast be published so that open source tools could be made that take advantage of these processes." I know of at least one place that grows their own wafers and does all their own processing, and publish absolutely nothing about it - no patents, no external papers, zip, zilch, nada - specifically because other people could read the patents and figure out what they were doing, so they keep it all trade secret. It gives them absolutely no advantage to publish about something it requires enormous capital costs to even be considering, it risks exposing some of their secret sauce, and it costs tens of millions of dollars (...a year) to develop and maintain - and you'd want them to what, give it away? For 'open source'? Open source hasn't even given us a competent PCB package, and has only recently given us a marginally passable office suite. In 2018. Let the magnitude of the utter failure of open source just sink in for a minute, there. Are people really that clueless, that they think "well, someone will take advantage of this if we just get people to publish about all the details that someone else spent all the money to create AND maintain!" I absolutely don't get the circle jerk for open source. It's amazing and wonderful at times, but let's not pretend it solves real problems. Elon Musk isn't going to open source his rocket designs anytime soon, but if you want a selection of 35000 poorly designed MP3 players, open source has your back!!112 If an open source solution solves a real problem, it was government funded (SPICE, LAPACK, MAXIMA, etc). We all paid for it. The one shining counterexample is the GNU Compiler - but FFS, they couldn't build a kernel even after the success of their compiler!
- loup-vaillant 9y ago> (One study found that the average commercial application contains 35 percent open-source code.) Yay! <Clicks the link> https://info.blackducksoftware.com/rs/872-OLS-526/images/OSSAReportFINAL.pdf https://info.blackducksoftware.com/rs/872-OLS-526/images/OSS... Nooo…