19 ms·

Quite different from a modern key debouncer circuit like http://zipcpu.com/blog/2017/08/04/debouncing.html http://zipcpu.com/blog/2017/08/04/debouncing.html .

Quite different from a modern key debouncer circuit like http://zipcpu.com/blog/2017/08/04/debouncing.html http://zipcpu.com/blog/2017/08/04/debouncing.html . The modern FPGA circuit first passes the input through two latches to synchronize it to the system clock, and then has a digital counter to add a delay to rapid bounces. Here the delay is analog, and there is no clock input: the output digital signal is still completely asynchronous. I wonder if they needed a second module to synchronize the signal and avoid metastability issues, or maybe that doesn't matter at the low clockspeeds they were using?

Bromskloss 9y ago
> The modern FPGA circuit first passes the input through two latches to synchronize it to the system clock, and then has a digital counter to add a delay to rapid bounces. What about debouncing with a low-pass filter, followed by a Schmitt trigger?
sehugg 9y ago
In a similar vein, old arcade games might debounce their coin detectors with two latches synchronized to, say, HSYNC/128 -- effectively giving a debounce of a few msec.
dfox 9y ago
That depends on environment you are working in. Digital debouncer in FPGA (or PLC for that matter) will involve some kind of digital timer as you cannot easily build simple RC low pass filter in such environment. In discrete logic debouncer designs with RC-filter that are quite similar to this tube circuit are still widely used and to some extent the modern designs are more similar to this when the schmitt trigger is realized as input of some MCU/FPGA and only external parts is the RC filter in contrast to tradditional discrete logic solutions which usually placed the filter between two schmitt trigger gates. By the way adding such external RC-filter (or even just series capacitor across the contacts) is quite cheap and quick fix for worn-out rotary encoders on various devices when existing (usually software) debouncing logic stops to be sufficient.

Bromskloss 9y ago

> The modern FPGA circuit first passes the input through two latches to synchronize it to the system clock, and then has a digital counter to add a delay to rapid bounces. What about debouncing with a low-pass filter, followed by a Schmitt trigger?

sehugg 9y ago

In a similar vein, old arcade games might debounce their coin detectors with two latches synchronized to, say, HSYNC/128 -- effectively giving a debounce of a few msec.

dfox 9y ago

That depends on environment you are working in. Digital debouncer in FPGA (or PLC for that matter) will involve some kind of digital timer as you cannot easily build simple RC low pass filter in such environment. In discrete logic debouncer designs with RC-filter that are quite similar to this tube circuit are still widely used and to some extent the modern designs are more similar to this when the schmitt trigger is realized as input of some MCU/FPGA and only external parts is the RC filter in contrast to tradditional discrete logic solutions which usually placed the filter between two schmitt trigger gates. By the way adding such external RC-filter (or even just series capacitor across the contacts) is quite cheap and quick fix for worn-out rotary encoders on various devices when existing (usually software) debouncing logic stops to be sufficient.