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The current miniaturization of DRAM circuitry doesn't really allow for a hardware fix for the RowHammer attack. During DRAM manufacturing a test similar to the
by hujji 9y ago
The current miniaturization of DRAM circuitry doesn't really allow for a hardware fix for the RowHammer attack. During DRAM manufacturing a test similar to the RowHammer attack exists. This test has certain bounds for passing. If the bounds were tightened up to the level of perfection to prevent the attack it would drop the yield a considerable amount.
- deleted 9y ago[deleted]
- userbinator 9y agoIf the bounds were tightened up to the level of perfection to prevent the attack it would drop the yield a considerable amount. The fact that DRAM older than a few years is effectively immune to RH suggests it is possible to manufacture such. Yes, it will cost more, but I think many would be willing to pay for it like they used to, for none other than the assurance of having more reliable memory.
- fiddlerwoaroof 9y agoIsn’t the problem related to the capacity of current memory modules? So you can have, say, a 32GB module that’s vulnerable or a 8GB module that isn’t? (Assuming the 8GB module uses lower density DRAM chips)
- HelloNurse 9y agoA new 8GB DIMM module has about 1/4 the silicon area of a new 32GB module and the same density (often 1/4 the number of identical chips); only an old 8GB module, made with an entirely different process, would have larger and less dense safer DRAM cells.
- fiddlerwoaroof 9y agoYeah, that's why I included the qualification
- joshtopher 9y agoI only buy DRAM that's aged at least 18 months
- bloaf 9y agoAren't some manufacturers better than others, though? https://arstechnica.com/information-technology/2016/03/once-thought-safe-ddr4-memory-shown-to-be-vulnerable-to-rowhammer/ https://arstechnica.com/information-technology/2016/03/once-...
- brokensegue 9y agomaybe add more bits of ECC?
- kps 9y agoOr indeed any bits of ECC. The fact that Intel omits or disables it on most CPUs is shameful.
- dboreham 9y agoThere's ECC inside the chips.
- Symmetry 9y agoThe internal caches have ECC but rowhammer targets the DIMMs. ECC DIMMs would solve the issue but Intel, for market segmentation reasons, fuses off the ability to handle ECC memory in consumer chips.
- baq 9y agoECC doesn't protect against rowhammer though. It makes it more difficult but not impossible.
- Dylan16807 9y agoIf you shut down whatever is triggering errors instead of completely ignoring them, the difficulty level is pretty close to "impossible".
- brokensegue 9y agoone bit of ECC isn't sufficient...
- kps 9y agoBest kind of correct… but modern wide memory controllers turned (9,8), which only detects one error, into (72,64), which is SECDED, “for free”.
- fulafel 9y agoThere are many examples of hardware using unreliable underlying layers, countered with whitening/scrambling, redudancy and other data encoding tricks. What would make RowHammer imprevious to these?
- JoshTriplett 9y agoThose tricks cost latency. You can get away with hiding some of that latency in access time to persistent storage. It's much harder to do so with RAM. ECC helps, and can be done at full rate, but isn't a complete solution for all possible problems. And anything you do in hardware at full RAM speed is expensive.
- fulafel 9y agoThis is far away from "hardware fix is impossible" though. In reputable hardware, hardware vendors are expected to maintain correctness in spite of performance advances. Also, DDR3/4 DRAM is glacially slow in latency terms, it's far from clear that there would be appreciable slowdown. There are already big latency compromises in the standardized JEDEC protocols that are not inherent in DRAM - it would be very two-faced for DRAM vendors to say they'll only trade off latency over backward compatibility or tiny cost savings, but not over correctness.
- olliej 9y agoThe trick I heard was to literally throttle the writes if you see repeated parallel writes or similar -- as row hammer depends on rapid writes that should be sufficient. But I also have no real idea how hardware actually works :) (magnets? how do they work?)
- Dylan16807 9y agoYou don't need to go that far at all. Just refresh neighbors occasionally when there are tons of accesses to the same place.
- rasz 9y agoYou dont have to overbuild silicon with huge margins, you can build rowhammer detection mechanism and force refresh when it triggers, thats what target row refresh is doing. Problem is Jedec didnt even bother enforcing it, instead making it optional :/