5 ms·

And day two: http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-day-two/ http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-...

by jabl 9y ago

AllSeeingEye 9y ago
"Boomv2 achieves 3.92 CoreMark/MHz (on the taped out BOOM), vs 3.71 for the Cortex-A9." - it's a bit of a letdown. I was hoping it'd be closer to x64 performance than to Cortex-A, but it's probably not achievable for RICS-V budget.
- phkahler 9y ago
  There is still a lot of low hanging fruit in the boom design. Hopefully Chris will still be contributing some improvement to Boom.
- asb 9y ago
  I'm sure Chris will drop by to expand this, but it should be noted that figure was for a particular instantiation. There's no reason you can't explore different power/performance/area trade-offs, or invest further development effort to further improve performance.
- _chris_ 9y ago
  Sorry to disappoint, AllSeeingEyes. What I taped out is a fairly modest instantiation of BOOM. I was trying to reduce risk and we had a very small area to play with, so I settled for ~4 CM/MHz. One potential win here would have been to use my TAGE-based predictor, which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies.
  - microcolonel 9y ago
    > which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies. Maybe these should be expressed as Instructions Per Second (at peak and at the point of diminishing returns?) or something like that, rather than two independent numbers. Higher clock frequency actually seems like a bad thing, all else being equal. It seems to me that throughput ought to trend toward infinity, clock frequency toward zero. ;- )
    - _chris_ 9y ago
      Of course it's important to always keep the "Iron Law" in mind, but it's far easier to compare ideas and talk about things in terms of IPC. For example, if a switch out one branch predictor for another, we're talking about an algorithmic change (implemented in hw) that will have an effect on IPC, and no effect on clock period (assuming we didn't screw something up). This is particularly useful when talking about a processor design, and not a specific processor in particular. As you said, there's a lot of good about slower clock frequencies, so you'll see the same ARM design being deployed at a variety of frequencies. Far easier to talk separately about a design's IPC from its achievable clock frequency (although both are important!).
  - AllSeeingEye 9y ago
    No worries, Chris, I didn't expect entirely new processor design to play in Intel league :) Really hoping to get my hands on RISC-V-based SBCs next year.
    - _chris_ 9y ago
      Me too!
- mtgx 9y ago
  Nobody is going to try to compete with Intel Core i7 or AMD Ryzen 7 from year one of a new ISA, for the same reason ARM chip makers didn't try to do that for years. It's just too risky and the investments need to be much bigger. Instead you "grow your way up" as ARM chips have done. Now, Cavium's Vulcan-based ThunderX2 seems to be beating Intel's Skylake server chips: https://www.nextplatform.com/2017/11/27/cavium-truly-contender-one-two-arm-server-punch/ https://www.nextplatform.com/2017/11/27/cavium-truly-contend...
  - monocasa 9y ago
    Cavium is still no where near intel on single core performance; they just threw way more simpler cores onto a chip.
    - mtgx 9y ago
      I can still see it as a great option for say shared hosting providers. Multiple times as many customers could be supported for the price they pay for Intel chips.
      - monocasa 9y ago
        Absolutely. Just saying that in the context of performance/cycle/core, they're closer to a bunch of Atoms than a Xeon (which, again, is totally fine for some use cases).
ajross 9y ago
Also: "Didn’t have the resources to support a customised register file. A synthesised register file resulted in huge congestion when routing the wires from the flip-flops. Instead, black-boxed the register file and hand-wrote some Verilog to instantiate specific flip-flops, muxes, and tri-state buffers. Effectively hand-crafting their own bit block out of standard cells." That just sounds insane to me that the tools can't handle synthesis of straightforward stuff like this. My personal fantasy startup is a next generation, mostly open-source EDA simulation, synthesis/optimization and place & route toolchain. You can expose the analog cell design to the world, but generate revenue from the per-fab process-specific partnering required to work the customers through the process of making real hardware. Who's got funding for me?
- phkahler 9y ago
  My comment on the register file is this: instead of making it 6r3w (6 read 3 write), just make it 2r3w and plop down 3 copies of it - each copy has 2 read ports feeding a local ALU and writes go to all instances. Then to add another ALU you make a 2r4w register file and plop down 4 instances of it - one connected to the new ALU. This is still only 6 ports total compared to 9 on the one they've got. Routing within the file should be much easier. The tradeoff is multiple instances of it.
  - sitkack 9y ago
    Area is the new clock speed.
    - StringyBob 9y ago
      Although not obvious to consumers, area has always been the bottom line - Gordon Moore used to call the biz 'expensive real estate' (about $1bn/acre)
  - ajross 9y ago
    Oh sure. But the text as I read it seemed to imply that the issue was the library they were using had hugely wasteful flip flops or something, or was unable to route above them, or something crazy. It seems (and I'm not expert or professional in this space) that everyone who's used these EDA tools has experiences like this, and hates them. Seems like a great target for innovation at a lower margin, especially now that ASIC development is becoming commoditized.
mtgx 9y ago
The security improvements are interesting. I hope they take DJB's advice into account when implementing the new crypto instructions and features: https://blog.cr.yp.to/20140517-insns.html https://blog.cr.yp.to/20140517-insns.html

And day two: http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-day-two/ http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-...

by jabl 9y ago

And day two: http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-day-two/ http://www.lowrisc.org/blog/2017/11/seventh-risc-v-workshop-...

AllSeeingEye 9y ago

"Boomv2 achieves 3.92 CoreMark/MHz (on the taped out BOOM), vs 3.71 for the Cortex-A9." - it's a bit of a letdown. I was hoping it'd be closer to x64 performance than to Cortex-A, but it's probably not achievable for RICS-V budget.

phkahler 9y ago
There is still a lot of low hanging fruit in the boom design. Hopefully Chris will still be contributing some improvement to Boom.
asb 9y ago
I'm sure Chris will drop by to expand this, but it should be noted that figure was for a particular instantiation. There's no reason you can't explore different power/performance/area trade-offs, or invest further development effort to further improve performance.
_chris_ 9y ago
Sorry to disappoint, AllSeeingEyes. What I taped out is a fairly modest instantiation of BOOM. I was trying to reduce risk and we had a very small area to play with, so I settled for ~4 CM/MHz. One potential win here would have been to use my TAGE-based predictor, which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies.
- microcolonel 9y ago
  > which is an easy >20% IPC improvement on Coremark. Of course, a lot more reworking would be needed to achieve x86-64 clock frequencies. Maybe these should be expressed as Instructions Per Second (at peak and at the point of diminishing returns?) or something like that, rather than two independent numbers. Higher clock frequency actually seems like a bad thing, all else being equal. It seems to me that throughput ought to trend toward infinity, clock frequency toward zero. ;- )
  - _chris_ 9y ago
    Of course it's important to always keep the "Iron Law" in mind, but it's far easier to compare ideas and talk about things in terms of IPC. For example, if a switch out one branch predictor for another, we're talking about an algorithmic change (implemented in hw) that will have an effect on IPC, and no effect on clock period (assuming we didn't screw something up). This is particularly useful when talking about a processor design, and not a specific processor in particular. As you said, there's a lot of good about slower clock frequencies, so you'll see the same ARM design being deployed at a variety of frequencies. Far easier to talk separately about a design's IPC from its achievable clock frequency (although both are important!).
- AllSeeingEye 9y ago
  No worries, Chris, I didn't expect entirely new processor design to play in Intel league :) Really hoping to get my hands on RISC-V-based SBCs next year.
  - _chris_ 9y ago
    Me too!
mtgx 9y ago
Nobody is going to try to compete with Intel Core i7 or AMD Ryzen 7 from year one of a new ISA, for the same reason ARM chip makers didn't try to do that for years. It's just too risky and the investments need to be much bigger. Instead you "grow your way up" as ARM chips have done. Now, Cavium's Vulcan-based ThunderX2 seems to be beating Intel's Skylake server chips: https://www.nextplatform.com/2017/11/27/cavium-truly-contender-one-two-arm-server-punch/ https://www.nextplatform.com/2017/11/27/cavium-truly-contend...
- monocasa 9y ago
  Cavium is still no where near intel on single core performance; they just threw way more simpler cores onto a chip.
  - mtgx 9y ago
    I can still see it as a great option for say shared hosting providers. Multiple times as many customers could be supported for the price they pay for Intel chips.
    - monocasa 9y ago
      Absolutely. Just saying that in the context of performance/cycle/core, they're closer to a bunch of Atoms than a Xeon (which, again, is totally fine for some use cases).

ajross 9y ago

Also: "Didn’t have the resources to support a customised register file. A synthesised register file resulted in huge congestion when routing the wires from the flip-flops. Instead, black-boxed the register file and hand-wrote some Verilog to instantiate specific flip-flops, muxes, and tri-state buffers. Effectively hand-crafting their own bit block out of standard cells." That just sounds insane to me that the tools can't handle synthesis of straightforward stuff like this. My personal fantasy startup is a next generation, mostly open-source EDA simulation, synthesis/optimization and place & route toolchain. You can expose the analog cell design to the world, but generate revenue from the per-fab process-specific partnering required to work the customers through the process of making real hardware. Who's got funding for me?

phkahler 9y ago
My comment on the register file is this: instead of making it 6r3w (6 read 3 write), just make it 2r3w and plop down 3 copies of it - each copy has 2 read ports feeding a local ALU and writes go to all instances. Then to add another ALU you make a 2r4w register file and plop down 4 instances of it - one connected to the new ALU. This is still only 6 ports total compared to 9 on the one they've got. Routing within the file should be much easier. The tradeoff is multiple instances of it.
- sitkack 9y ago
  Area is the new clock speed.
  - StringyBob 9y ago
    Although not obvious to consumers, area has always been the bottom line - Gordon Moore used to call the biz 'expensive real estate' (about $1bn/acre)
- ajross 9y ago
  Oh sure. But the text as I read it seemed to imply that the issue was the library they were using had hugely wasteful flip flops or something, or was unable to route above them, or something crazy. It seems (and I'm not expert or professional in this space) that everyone who's used these EDA tools has experiences like this, and hates them. Seems like a great target for innovation at a lower margin, especially now that ASIC development is becoming commoditized.

mtgx 9y ago

The security improvements are interesting. I hope they take DJB's advice into account when implementing the new crypto instructions and features: https://blog.cr.yp.to/20140517-insns.html https://blog.cr.yp.to/20140517-insns.html