7 ms·

According to the table in the article: - 2011: 32nm - 2012: 22nm - 2014: 14nm - 2018?: 10nm I don't know much about foundry processes, but it seems that it

by GuiA 9y ago

According to the table in the article: - 2011: 32nm - 2012: 22nm - 2014: 14nm - 2018?: 10nm I don't know much about foundry processes, but it seems that it's taking more and more time for lesser and lesser gains, right? At this rate, how long until we reach sub nanometer? What are the physical limits on these processes, and does it have any implications for end users? Will we be using 2nm CPUs for 50 years? Would love to hear the thinking of anyone educated on the topic. Edit: very intrigued by the sustained downvotes on this ¯\_(ツ)_/¯

spydum 9y ago
widely assumed 5nm is the limit. I know i've seen others discuss some ideas around how close they can get, but i'm struggling to find the thread.. In any case, this may help: https://en.wikipedia.org/wiki/5_nanometer https://en.wikipedia.org/wiki/5_nanometer Found it.. http://semiengineering.com/will-7nm-and-5nm-really-happen/ http://semiengineering.com/will-7nm-and-5nm-really-happen/ and the HN discussion from several years ago: https://news.ycombinator.com/item?id=7920108 https://news.ycombinator.com/item?id=7920108
- SemiTom 9y ago
  also Is 7nm The Last Major Node? https://semiengineering.com/7nm-last-major-node/ https://semiengineering.com/7nm-last-major-node/
jacquesm 9y ago
The step from 14 to 10 nm is huge. Both from a technological perspective on the manufacturing side as well as on the effect it will have to the number of transistors on a die and the power consumption of those transistors. Remember that power consumption and the number of transistors are related to the surface area so there is a square factor in there. 14 nm ^2 = 196, 10 nm ^2 = 100, so that's almost a doubling of the number of transistors and approximately a halving of the power required per transistor for a given die area.
- Osmium 9y ago
  While true, the same math holds for 22 nm^2 (484) to 14 nm^2 (196). Real world gains will never be as high as the math suggests, as you get into leakage currents etc.
  - jacquesm 9y ago
    Sure, I never meant to imply that previous process steps were much smaller, just that this one is still formidable in its own right. Real world gains will not be 100% but they're a very large fraction of that. Obviously any technological advance in a mature industry is going to show reduced return on investment at some point, it's rather surprising that the ROI on these process shrinks is still worth it given that we are now well beyond what was thought to be possible not all that long ago.
- deepnotderp 9y ago
  Okay, so the node names are effectively useless at this point. They used to refer to gate length, but no longer, even for Intel. Oh, and Intel's 10nm will actually have lower performance than their 14nm. Besides, it matters not, the bottlenecks today are in memory and interconnects.
  - Dylan16807 9y ago
    > Oh, and Intel's 10nm will actually have lower performance than their 14nm. Less than 14++, sure, but 10+ and 10++ will fix that.
    - deepnotderp 9y ago
      Yes, but I was just pointing out that scaling is now neither a panacea nor free.
  - ktRolster 9y ago
    At some point, maybe we'll start seeing RAM put onto the CPU itself. I mean, more than it already is (with cache).
rayiner 9y ago
There are various limits in play: https://www.extremetech.com/computing/97469-is-14nm-the-end-of-the-road-for-silicon-lithography https://www.extremetech.com/computing/97469-is-14nm-the-end-.... At sub-nanometer we're talking about features of 5-10 atoms across. At that scale you get effects like electrons quantum tunneling between transistors: https://www.theverge.com/circuitbreaker/2016/10/6/13187820/one-nanometer-transistor-berkeley-lab-moores-law https://www.theverge.com/circuitbreaker/2016/10/6/13187820/o.... We probably won't get there with existing silicon technology.
- TheSpiceIsLife 9y ago
  I read on HN, a couple months ago, these numbers no longer represent the physical size of anything but are now just a marketing label, a sort of 'performance equivalent to a theoretical size of'. Anyone know if there's any truth to this? Might try to find the comment later when I have time.
  - 0xcde4c3db 9y ago
    I don't have any direct experience with "deep submicron" stuff, but from what I've read you basically can't trust these numbers to be comparable. The various sizes/spacings don't scale together the way they did for larger feature sizes, so you could have e.g. a "14nm" process where the area of an SRAM cell, NAND gate etc. ends up the same size as another foundry's "20nm" process even though the actual transistors are smaller.
  - aslkdjaslkdj 9y ago
    Intel's are actual measurements. TSMC, GF, and samsung are all marketing bs.
    - deepnotderp 9y ago
      They're all marketing, Intel is no exception. At 40nm and over, the Intel node names were larger than the industry average, now it's the other way around.
  - 9y ago
wereHamster 9y ago
Going from 14nm to 10nm increases the number of transistors per mm from 37 to 100 millions. That's a huge difference!!
leggomylibro 9y ago
I think that beyond our current processes, there is the potential for different materials to take the place of XXnm silicon processes, which could fit more transistors in a smaller area. Research like: http://news.stanford.edu/press-releases/2017/08/11/new-ultrathin-sens-secret-powers http://news.stanford.edu/press-releases/2017/08/11/new-ultra... "3D" processes which build multiple layers on top of one another may also see more investment as other methods become prohibitively expensive. And once you've cheaply gone to 2 layers in a big blob of epoxy, what's stopping you from doing 4? 8? 16? 32? [Heat dissipation, probably] But whatever, people have been saying Moore's Law is dead since Moore's Law was invented. Who knows whether we'll technically hit one milestone or another. Things get faster, what the hell.
- nhaehnle 9y ago
  People are already stacking multiple layers today for memory, although the layers are always manufactured separately and then bonded together in a separate step. I wouldn't be surprised to see more of that in the future, think caches on top of cores, but I doubt we'll ever see multiple layers of transistors produced in a single step. Technical challenges aside, the economics of trying to produce multiple layers at once are just always going to be worse: higher latency from a wafer entering a fab to finishing the wafer, and much higher rate of defects. (When you produce the layers separately, you can potentially test them separately before putting them together, which is a huge win for defect rate.) It's possible that manufacturing multiple layers at once might eventually allow for a higher density of vertical interconnects, but I just don't see that becoming the deciding factor.
ijidak 9y ago
This is a sensible question. Not sure either why the downvotes. I'm curious as to the answer myself. Although, I don't know if we'll ever see sub-nanometer. Maybe that's the reason for the downvotes, that sub-nanometer is not really in the realm of what's possible with current CPU architectures and the physics of silicon. Although, that's simply based on today's physics. Who truly knows what the future will bring.
Dolores12 9y ago
If you consider relative change it looks like 2011: 32nm 2012: 31% size reduction 2014: 36% size reduction 2018: 28,5% size reduction
- GuiA 9y ago
  Yes, but in 1, 2, and 4 years respectively.
  - Dolores12 9y ago
    In 8 years, in 2026, we expect 7nm.
jabl 9y ago
> I don't know much about foundry processes, but it seems that it's taking more and more time for lesser and lesser gains, right? At this rate, how long until we reach sub nanometer? What are the physical limits on these processes, and does it have any implications for end users? Will we be using 2nm CPUs for 50 years? The lattice constant of crystalline silicon is 0.54 nm, and since it's an FCC structure the distance between neighboring atoms is 0.38 nm. So with a hypothetical 2 nm CPU, some feature would be only roughly 5 atoms across, which leaves VERY little room for manufacturing tolerance. How would one manufacture a device containing billions of transistors with such small tolerances? I don't think we'll ever see such things, at least not with a lithography approach. Heck, I think it's close to black magic that they are able to produce transistors on a 10nm process, but apparently experts say that up to 5nm (13 atoms!!!) might be possible.
bullen 9y ago
All you get now is power reduction. Performance is completely bottlenecked since 22nm. Peak computing!
mtgx 9y ago
Didn't 14nm arrive late 2015 or in 2016?

by GuiA 9y ago

spydum 9y ago

widely assumed 5nm is the limit. I know i've seen others discuss some ideas around how close they can get, but i'm struggling to find the thread.. In any case, this may help: https://en.wikipedia.org/wiki/5_nanometer https://en.wikipedia.org/wiki/5_nanometer Found it.. http://semiengineering.com/will-7nm-and-5nm-really-happen/ http://semiengineering.com/will-7nm-and-5nm-really-happen/ and the HN discussion from several years ago: https://news.ycombinator.com/item?id=7920108 https://news.ycombinator.com/item?id=7920108

SemiTom 9y ago
also Is 7nm The Last Major Node? https://semiengineering.com/7nm-last-major-node/ https://semiengineering.com/7nm-last-major-node/

jacquesm 9y ago

The step from 14 to 10 nm is huge. Both from a technological perspective on the manufacturing side as well as on the effect it will have to the number of transistors on a die and the power consumption of those transistors. Remember that power consumption and the number of transistors are related to the surface area so there is a square factor in there. 14 nm ^2 = 196, 10 nm ^2 = 100, so that's almost a doubling of the number of transistors and approximately a halving of the power required per transistor for a given die area.

Osmium 9y ago
While true, the same math holds for 22 nm^2 (484) to 14 nm^2 (196). Real world gains will never be as high as the math suggests, as you get into leakage currents etc.
- jacquesm 9y ago
  Sure, I never meant to imply that previous process steps were much smaller, just that this one is still formidable in its own right. Real world gains will not be 100% but they're a very large fraction of that. Obviously any technological advance in a mature industry is going to show reduced return on investment at some point, it's rather surprising that the ROI on these process shrinks is still worth it given that we are now well beyond what was thought to be possible not all that long ago.
deepnotderp 9y ago
Okay, so the node names are effectively useless at this point. They used to refer to gate length, but no longer, even for Intel. Oh, and Intel's 10nm will actually have lower performance than their 14nm. Besides, it matters not, the bottlenecks today are in memory and interconnects.
- Dylan16807 9y ago
  > Oh, and Intel's 10nm will actually have lower performance than their 14nm. Less than 14++, sure, but 10+ and 10++ will fix that.
  - deepnotderp 9y ago
    Yes, but I was just pointing out that scaling is now neither a panacea nor free.
- ktRolster 9y ago
  At some point, maybe we'll start seeing RAM put onto the CPU itself. I mean, more than it already is (with cache).

rayiner 9y ago

There are various limits in play: https://www.extremetech.com/computing/97469-is-14nm-the-end-of-the-road-for-silicon-lithography https://www.extremetech.com/computing/97469-is-14nm-the-end-.... At sub-nanometer we're talking about features of 5-10 atoms across. At that scale you get effects like electrons quantum tunneling between transistors: https://www.theverge.com/circuitbreaker/2016/10/6/13187820/one-nanometer-transistor-berkeley-lab-moores-law https://www.theverge.com/circuitbreaker/2016/10/6/13187820/o.... We probably won't get there with existing silicon technology.

TheSpiceIsLife 9y ago
I read on HN, a couple months ago, these numbers no longer represent the physical size of anything but are now just a marketing label, a sort of 'performance equivalent to a theoretical size of'. Anyone know if there's any truth to this? Might try to find the comment later when I have time.
- 0xcde4c3db 9y ago
  I don't have any direct experience with "deep submicron" stuff, but from what I've read you basically can't trust these numbers to be comparable. The various sizes/spacings don't scale together the way they did for larger feature sizes, so you could have e.g. a "14nm" process where the area of an SRAM cell, NAND gate etc. ends up the same size as another foundry's "20nm" process even though the actual transistors are smaller.
- aslkdjaslkdj 9y ago
  Intel's are actual measurements. TSMC, GF, and samsung are all marketing bs.
  - deepnotderp 9y ago
    They're all marketing, Intel is no exception. At 40nm and over, the Intel node names were larger than the industry average, now it's the other way around.
- 9y ago

wereHamster 9y ago

Going from 14nm to 10nm increases the number of transistors per mm from 37 to 100 millions. That's a huge difference!!

leggomylibro 9y ago

I think that beyond our current processes, there is the potential for different materials to take the place of XXnm silicon processes, which could fit more transistors in a smaller area. Research like: http://news.stanford.edu/press-releases/2017/08/11/new-ultrathin-sens-secret-powers http://news.stanford.edu/press-releases/2017/08/11/new-ultra... "3D" processes which build multiple layers on top of one another may also see more investment as other methods become prohibitively expensive. And once you've cheaply gone to 2 layers in a big blob of epoxy, what's stopping you from doing 4? 8? 16? 32? [Heat dissipation, probably] But whatever, people have been saying Moore's Law is dead since Moore's Law was invented. Who knows whether we'll technically hit one milestone or another. Things get faster, what the hell.

nhaehnle 9y ago
People are already stacking multiple layers today for memory, although the layers are always manufactured separately and then bonded together in a separate step. I wouldn't be surprised to see more of that in the future, think caches on top of cores, but I doubt we'll ever see multiple layers of transistors produced in a single step. Technical challenges aside, the economics of trying to produce multiple layers at once are just always going to be worse: higher latency from a wafer entering a fab to finishing the wafer, and much higher rate of defects. (When you produce the layers separately, you can potentially test them separately before putting them together, which is a huge win for defect rate.) It's possible that manufacturing multiple layers at once might eventually allow for a higher density of vertical interconnects, but I just don't see that becoming the deciding factor.

ijidak 9y ago

This is a sensible question. Not sure either why the downvotes. I'm curious as to the answer myself. Although, I don't know if we'll ever see sub-nanometer. Maybe that's the reason for the downvotes, that sub-nanometer is not really in the realm of what's possible with current CPU architectures and the physics of silicon. Although, that's simply based on today's physics. Who truly knows what the future will bring.

Dolores12 9y ago

If you consider relative change it looks like 2011: 32nm 2012: 31% size reduction 2014: 36% size reduction 2018: 28,5% size reduction

GuiA 9y ago
Yes, but in 1, 2, and 4 years respectively.
- Dolores12 9y ago
  In 8 years, in 2026, we expect 7nm.

jabl 9y ago

> I don't know much about foundry processes, but it seems that it's taking more and more time for lesser and lesser gains, right? At this rate, how long until we reach sub nanometer? What are the physical limits on these processes, and does it have any implications for end users? Will we be using 2nm CPUs for 50 years? The lattice constant of crystalline silicon is 0.54 nm, and since it's an FCC structure the distance between neighboring atoms is 0.38 nm. So with a hypothetical 2 nm CPU, some feature would be only roughly 5 atoms across, which leaves VERY little room for manufacturing tolerance. How would one manufacture a device containing billions of transistors with such small tolerances? I don't think we'll ever see such things, at least not with a lithography approach. Heck, I think it's close to black magic that they are able to produce transistors on a 10nm process, but apparently experts say that up to 5nm (13 atoms!!!) might be possible.

bullen 9y ago

All you get now is power reduction. Performance is completely bottlenecked since 22nm. Peak computing!

mtgx 9y ago

Didn't 14nm arrive late 2015 or in 2016?