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Who is this author? This seems mostly wrong to me. Shrinking die size doesn't seem to have anything to do with the removal of tristate buffers from FPGAs. FPGA
by davemp 9y ago
Who is this author? This seems mostly wrong to me. Shrinking die size doesn't seem to have anything to do with the removal of tristate buffers from FPGAs. FPGA vendors are constently trying to shorten the length/amount of interconnects because it translates into faster designs with more logic regardless of die size.
What what I've heard/read. The RAM change is entirely due to architectural improvements and a shift towards "columnar" design. Architects have learned that having your data flow in a similar direction simplifies routing and leads to more dense and faster designs.
The pattern:
LOGIC <- CONTROLLER <=> RAM
Doesn't translate well to modern FPGA architectures because of the multiple data directions, so architects switched to:
INPUT/CONTROLLER -> RAM -> READ_LOGIC
* This is a simplification as FPGAs place and route is a pretty huge problem with many trades offs to consider.
- chclau 9y agoI am the author of the article and it may seem wrong to you but it is the way things unfolded. Once interconnections were faster than the transistors, at the beginning of the 2000's that fact was reverted, now transistors are much faster than interconnection. It is the reason behind many other development, like multi-core devices. Since transistors are faster than interconnections, it is reasonable to make many units working fast than a big unit working slower because of the interconnections. The tristate buffers were abandoned on the FPGA market, followed by the ASIC market.
- davemp 9y agoSorry, you are definately right about the motivation for the change. My first paragraph is off base. I should have said "this seems incomplete" instead of wrong. I just wanted to see the architectual reasoning behind how switching from tristate -> unidirectional leads to faster interconnects.