So the issue is that you can't get an invariant TSC without Ring-0 access? I assumed AMD already had invariant TSC before Ryzen that was accessible from userspa

So the issue is that you can't get an invariant TSC without Ring-0 access? I assumed AMD already had invariant TSC before Ryzen that was accessible from userspace. Certainly Intel has had that since Nehalem if I recall. It just seems an odd thing to be hard considering how important it is. I never thought about it being a cycle count since I usually access via a wrapper. I guess the wrappers are converting from cycles to nanoseconds.