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Intels "real clock" is `TSC`. This counts processor cycles. SandyBridge (and up, I think) ensure the `TSC` value never fluctuates but remains constant (at CPUID
by valarauca1 9y ago
Intels "real clock" is `TSC`. This counts processor cycles. SandyBridge (and up, I think) ensure the `TSC` value never fluctuates but remains constant (at CPUID quoted clock speedish). Generally this _real clock_ is called `RDTSC` even tho its still `TSC` instruction.
Some rumblings from Intel suggest they may discontinue this. Either way this is addressed
`APERF` seems to be AMD's version of `RDTSC` but that requires the code execute in Ring-0. So it sounds like Agner was building a kernel module to wrap the existing test suite.
- zlynx 9y agoFrom the article I think that's backward. AMD's RDTSC is a constant-rate cycle counter and APERF counts actual cycles. So with clock boosting from XFR, etc, APERF will increase while RDTSC will not.
- arielweisberg 9y agoSo the issue is that you can't get an invariant TSC without Ring-0 access? I assumed AMD already had invariant TSC before Ryzen that was accessible from userspace. Certainly Intel has had that since Nehalem if I recall. It just seems an odd thing to be hard considering how important it is. I never thought about it being a cycle count since I usually access via a wrapper. I guess the wrappers are converting from cycles to nanoseconds.