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I last did either VHDL or Verilog in 1997, which is 20 years ago (and reminds me I'm getting old), but if things are remotely similar, the apt comparison is not
by beagle3 10y ago
I last did either VHDL or Verilog in 1997, which is 20 years ago (and reminds me I'm getting old), but if things are remotely similar, the apt comparison is not ARM assembly vs. MIPS assembly, but rather Verilog=~C vs VHDL=~Ada
- chclau 10y agoI don't know ADA, I have always thought that Verilog is like old C and VHDL like C++. Not that VHDL is object oriented, but is a strong-typed language.
- beagle3 10y agoVHDL's syntax was borrowed from Ada (and much more closely resembles it than Verilog, which was inspired by C but not adapted from it) Example Ada: http://perso.telecom-paristech.fr/~pautet/Ada95/e_c16_p5.ada http://perso.telecom-paristech.fr/~pautet/Ada95/e_c16_p5.ada
- ajdlinux 10y agoVHDL's syntax and type system are quite Ada-ish, from what I gather.
- oelang 10y agoVHDL is an old version of ADA combined with a build-in discrete event simulator. The syntax, type system, general semantics are all copied from ADA. This is actually a good thing, Verilog (and even more SystemVerilog) is designed by people who don't have a clue about language design resulting in an incredible mess of a language.