For many years now I have been using mainly Altera and VHDL. Lately I started a new job and returned to Xilinx which I have not used for long. Part of my job is

For many years now I have been using mainly Altera and VHDL. Lately I started a new job and returned to Xilinx which I have not used for long. Part of my job is integrating three major IPs, and guess what? One of them is VHDL and two others are Verilog. So yes, sure, you can wrap a Verilog code with VHDL and forget it... but, the Verilog IPs come also with their Verilog testbenches, etc. So for me it will be a bilingual reality for some time to come.