2 ms·
You're ignoring a lot of context being created by the parent comment. While the latencies may never directly compete with DRAM, planned densities are already mo
by _wmd 9y ago
You're ignoring a lot of context being created by the parent comment. While the latencies may never directly compete with DRAM, planned densities are already more than favourable. Having a 2TB chunk of persistent memory mapped into your address space with single-thread performance exceeding 100,000 random reads/sec with extremely consistent latency is a game-changer in for example database applications.
- Dylan16807 9y agoWhat context am I missing? While Analemma_ was talking about using it to augment DRAM, like you are, endorphone was very specifically talking about replacing DRAM in that comment. And that comment claims that it already has good enough latency for the job.
- endorphone 9y agoIt's turtles all the way down, and I think this is needlessly splitting hairs. L1->L2->L3->(L4->)DRAM->Storage 3D XPoint is being considered as the DIMM-module, byte-addressed "memory" before storage. Saying that it "augments" DRAM is almost meaningless because we already have multiple levels of DRAM.
- davrosthedalek 9y agoIf I am not mistaken, we have only one level of DRAM. Caches are SRAM. (Also, DRAM on DIMM is not byte-addressable)
- cocoablazing 9y agoThe PS2, Xbox 360, Wii, and some intel chips with iris provide on-die DRAM caches.