3 ms·

3D XPoint has extremely low latency (e.g. 7 usec), and has already been demonstrated as such. Putting it through a PCI slot and a storage controller is not the

3D XPoint has extremely low latency (e.g. 7 usec), and has already been demonstrated as such. Putting it through a PCI slot and a storage controller is not the same. The discussion is about running it as DIMM memory through a normal memory controller.

Dylan16807 10y ago
So you remove the storage controller and PCIe bus and you go from 10us to 7us. 7us is still a hundred times slower than DRAM, is it not?
- _wmd 10y ago
  You're ignoring a lot of context being created by the parent comment. While the latencies may never directly compete with DRAM, planned densities are already more than favourable. Having a 2TB chunk of persistent memory mapped into your address space with single-thread performance exceeding 100,000 random reads/sec with extremely consistent latency is a game-changer in for example database applications.
  - Dylan16807 10y ago
    What context am I missing? While Analemma_ was talking about using it to augment DRAM, like you are, endorphone was very specifically talking about replacing DRAM in that comment. And that comment claims that it already has good enough latency for the job.
    - endorphone 10y ago
      It's turtles all the way down, and I think this is needlessly splitting hairs. L1->L2->L3->(L4->)DRAM->Storage 3D XPoint is being considered as the DIMM-module, byte-addressed "memory" before storage. Saying that it "augments" DRAM is almost meaningless because we already have multiple levels of DRAM.
      - davrosthedalek 10y ago
        If I am not mistaken, we have only one level of DRAM. Caches are SRAM. (Also, DRAM on DIMM is not byte-addressable)
        cocoablazing 10y ago
        The PS2, Xbox 360, Wii, and some intel chips with iris provide on-die DRAM caches.
- endorphone 10y ago
  It's about 30 times slower than the real-world latency of RAM, which is obviously a problem but it's one that caching might resolve (e.g. an L4 of 32GB of GDDR5)

Dylan16807 10y ago

So you remove the storage controller and PCIe bus and you go from 10us to 7us. 7us is still a hundred times slower than DRAM, is it not?

_wmd 10y ago
You're ignoring a lot of context being created by the parent comment. While the latencies may never directly compete with DRAM, planned densities are already more than favourable. Having a 2TB chunk of persistent memory mapped into your address space with single-thread performance exceeding 100,000 random reads/sec with extremely consistent latency is a game-changer in for example database applications.
- Dylan16807 10y ago
  What context am I missing? While Analemma_ was talking about using it to augment DRAM, like you are, endorphone was very specifically talking about replacing DRAM in that comment. And that comment claims that it already has good enough latency for the job.
  - endorphone 10y ago
    It's turtles all the way down, and I think this is needlessly splitting hairs. L1->L2->L3->(L4->)DRAM->Storage 3D XPoint is being considered as the DIMM-module, byte-addressed "memory" before storage. Saying that it "augments" DRAM is almost meaningless because we already have multiple levels of DRAM.
    - davrosthedalek 10y ago
      If I am not mistaken, we have only one level of DRAM. Caches are SRAM. (Also, DRAM on DIMM is not byte-addressable)
      - cocoablazing 10y ago
        The PS2, Xbox 360, Wii, and some intel chips with iris provide on-die DRAM caches.
endorphone 10y ago
It's about 30 times slower than the real-world latency of RAM, which is obviously a problem but it's one that caching might resolve (e.g. an L4 of 32GB of GDDR5)