Hahahaha, No. Synthesizing ASICs and FPGA designs from Verilog/VHDL/insertnewhighlevellanguagehere may be close to software, but I guarantee you that creating

Hahahaha, No. Synthesizing ASICs and FPGA designs from Verilog/VHDL/insertnewhighlevellanguagehere may be close to software, but I guarantee you that creating high end production chips with such strict efficiency constraints guarantees that you need to do heavy simulations, and most importantly, has massive verification (it is 10/7nm after all....) efforts.