13 ms·
AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2
- throwawayish 10y agoI think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive applications. Overall it seems that Sun with it's Niagara-approach (massive number of threads, lots of I/O on-chip) was just a few years too early (and likely a few thousands / system to expensive ;)
- gigatexal 10y agoLet's hope this isn't niagra again: it needs to have decent clock speeds as IPC is still worth something today. But yes, I totally agree, this is an exciting chip.
- alimbada 10y agoNaples is based on Ryzen which, if you look at early benchmarks, is beating the competition on all fronts except gaming (suspectedly due to software optimisation and motherboard issues).
- gigatexal 10y agoyes but four modules of ryzen to make this beastly naples chip isn't going to be clocked at the same frequencies. the top end intel chips have TDPs of 165W but 4 ryzen chips at 3.6ghz have a tdp of 65w a piece and you're not going to see a 260W server chip if you want to sell into the datacenter.
- Tostino 10y agoI can see a use case for it, as long as it delivers on performance. No one minds high TDP, as long as it offers a performance advantage. Hell, some servers have 4-8 Titans in them, and no one is complaining about their TDP. If a 260W CPU TDP is justified by the performance, no one will care.
- gigatexal 10y agoI'm more than willing to admit I could be wrong. And maybe Intel will push the TDP envelope with servers as well if Naples proves a threat when things all shake out. Just if Intel hasn't put a ~250W server chip into production I doubt AMD will then again if it performs that much better then there's a calculus there that will need to be done. My prediction, based on no evidence, is that this 32-core chip will be clocked at 2.6ghz and boost to 3.2. Shot in the dark, but given current TDPs that's where I think things might shake out to.
- kayoone 10y agomaybe for single server or academia setups, but in datacenters TDP and power consumption absolutely do matter.
- gigatexal 10y agoAnd that was my point as well.
- throwawayish 10y agoThe bigger E7 scratch the 200 W mark pretty hard and IBM already had POWER chips go beyond 200 W. However, cooling and power density are ... problematic. The same goes for accelerators. Supermicro will happily deliver you a 1U box with four pascals and two Xeon sockets, but there is no datacenter in the world were you can stuff 42 of those in a cabinet. [Which doesn't mean that these don't make sense] However, high end systems don't lend themselves well to mass-deployment (i.e. scale out).
- striking 10y ago
- binarycrusader 10y agoIt's not, not only did AMD move from CMT (clustered multi-thread) design used in the previous Bulldozer microarchitecture, they now have an SMT (simultaneous multithreading) architecture allowing for 2 threads per core. By comparison, the performance of sparc substantially improved moving from the T1, T2 to T3+. The T1 used a round-robin policy to issue instructions from the next active thread each cycle, supporting up to 8 fine-grained threads in total. That made it more like a barrel processor. Starting with the T3, two of the threads could be executed simultaneously. Then, starting with the T4, sparc added dynamic threading and out-of-order execution. Later versions are even faster and clock speeds have also risen considerably.
- gigatexal 10y agoI didn't know about this. Are there benchmarks that aren't canned by Oracle that you know of? I'm intrigued by this round-robin way of threading. I'm not a cpu expert, but how does this compare with the Power arch's way of threading?
- deleted 10y ago[deleted]
- jabl 10y agoThink of it this way, the original Niagara (T1) was an in-order CPU. That is, instructions were executed in the order they occur in the program code. This is simple and power efficient but doesn't produce very good single thread performance, since the processor stalls if an instruction takes longer than expected. Say, a load instruction misses L1 cache and has to fetch the data from L2/L3/Lwhatever/memory. Now, one way to drive up the utilization of the CPU core is to add hardware threads. And the simplest way to do that? Well, just run an instruction from another available thread every cycle (that is, if a thread is blocked e.g. waiting for memory, skip it). So now you have a CPU that is still pretty small, simple and power efficient, but can still exploit memory level parallelism (i.e. have multiple outstanding memory ops in flight). Now, the other approach, is that you have a CPU with out of order (OoO) execution. Meaning that the CPU contains a scheduler that handles a queue of instructions, and any instruction that has all its dependencies satisfied can be submitted for execution. And then later on a bunch of magic happens so that externally to the CPU it still looks like everything was executed in order like the program code specified. This is pretty good for getting good single thread performance, and can exploit some amount of MLP as well, e.g. if a bunch of instructions are waiting for a memory operation to complete, some other instructions can still proceed (perhaps executing a memory op themselves). So in this model the amount of MLP is limited by the inherent serial dependencies in the code, and on the length of the instruction queues that the scheduler maintains. The downside of this is that the OoO logic takes up quite a bit of chip area (making it more expensive), and also tends to be one of the more power-hungry parts of the chip. But, if you want good single-thread performance, that's the price you have to pay.. Anyway, now that you have this OoO CPU, what about adding hardware threads? Well, now that you already have all this scheduling logic, turns out it's relatively easy. Just "tag" each instruction with a thread ID, and let the scheduler sort it all out. So this is what is called Simultaneous Multi-Threading (SMT). So in a way it's a pretty different way of doing threading compared to the Niagara-style in-order processor. Also, since you already have all this OoO logic that is able to exploit some MLP within each thread, you don't need as many threads as the Niagara-style CPU to saturate the memory subsystem. So, this SMT style of threading is what you see in contemporary Intel x86 processors (they call it hyperthreading (HT)), IBM POWER, and now also AMD Zen cores. As for benchmarks, I'm too lazy to search, but I'm sure you can find e.g. some speccpu results for Niagara.
- mtgx 10y agoIntel doesn't have SHA2 acceleration? ARMv8 has had it for like 2-3 years now... And AMD should dump SHA1 acceleration in the next generation.
- throwawayish 10y agoARM cores are much weaker, crypto performance without NEON is absymal across the board. Of course, compared to hardware-acceleration software always seems slow; Haswell manages AES-OCB at <1 cpb.
- drzaiusapelord 10y ago>And AMD should dump SHA1 acceleration in the next generation. The cost to have that on silicon is probably close to zero. If you think SHA1 is just going to magically disappear because you want it to, well, you'll be in for a SHA1 sized surprise. Our grandkids will still have SHA1 acceleration. >ARMv8 has had it for like 2-3 years now... Because ARM cores don't remotely have the CPU heft an Intel x86/64 chip has, so ARM needs all this acceleration because its typically used in very low power mobile scenarios. On top of that, Intel claims AES-NI can be used to accelerate SHA1. https://software.intel.com/en-us/articles/improving-the-performance-of-the-secure-hash-algorithm-1 https://software.intel.com/en-us/articles/improving-the-perf...
- istoica 10y agoWhy should it be dropped ? Isn't it just a hash function ?
- pjc50 10y agoIf you remove things from the instruction set, any code that uses them will either crash or run very slowly in emulation. Most uses of special instructions will check feature bits or CPU version, but not all will do so correctly. (I'd say that the additional area cost of something like this is small, and the big cost of special instructions is reserving opcodes and feature bits)
- AYBABTME 10y ago
- tw04 10y agoIntel hass had SHA1/2 acceleration for YEARS via the AES-NI instruction set. https://en.wikipedia.org/wiki/Intel_SHA_extensions https://en.wikipedia.org/wiki/Intel_SHA_extensions >There are seven new SSE-based instructions, four supporting SHA-1 and three for SHA-256: >SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2, SHA256RNDS2, SHA256MSG1, SHA256MSG2
- floatboth 10y agohaha nope. This is not a part of AES-NI. The only processors so far with these extensions are low power Goldmont chips. https://github.com/weidai11/cryptopp/issues/139 https://github.com/weidai11/cryptopp/issues/139
- Scaevolus 10y agoGoldmont probably has them because it doesn't have the wide AVX pipelines necessary for fast software crypto. Skylake can compute SHA1 at 4.3-3.4 cycles/B and SHA256 at 7-9 cycles/B [1]. That's ~1GB/s SHA1 and ~500MB/s SHA256. 1: https://bench.cr.yp.to/results-hash.html#amd64-skylake https://bench.cr.yp.to/results-hash.html#amd64-skylake
- throwawayish 10y agoThis is not part of AES-NI and has never been released in a mid-range+ server/desktop CPU, only part of some Atom parts (Goldmont). Therefore software support is poor (I think OpenSSL does not support it). It is said to be included in 2018+ Cannonlake, though.
- semi-extrinsic 10y ago> 128 PCIe lanes in a 1S system is unprecedented Yes, definitely drooling at this. Assuming a workload that doesn't eat too much CPU, this would make for a relatively cheap and hassle-free non-blocking 8 GPU @ 16x PCIe workstation. I wants one.
- sorenjan 10y agoThat does sound pretty spectacular, and really loud. What kind of case would you put that in? Would you work with ear protection?
- semi-extrinsic 10y agoWrt. noise: decibels (dB, "perceived loudness") are logarithmic in sound energy, so going from e.g. a single GTX 1080 at 47 dB to 8x GTX 1080 only increases the noise to 56 dB, which is noticeable but not really annoying, and very far from requiring ear protection. Recommendations for office spaces is that noise be kept < 60 dB IIRC. Wrt. cases: I think a regular E-ATX compatible case should be enough, but it all depends on the motherboard, and those don't exist yet. Existing 8x GPU servers have been 4U rack mount dual socket affairs; you can also already get 7x GPU dual socket "EEB" motherboards and workstation style cases, but none that will do full 16x for all the GPUs.
- kogepathic 10y ago> Recommendations for office spaces is that noise be kept < 60 dB IIRC. I'd quit if I had to work in an office space with 60 dB noise. That's like sitting next to a rack of 1U servers at "moderately angry bee swarm" fan level. I personally cannot stand to be near a noise source above 40 dB for any extended length of time (more than a few hours). But 60 dB... wow. Can't imagine how shitty that must be to work in for 8 hours per day.
- JorgeGT 10y agoSeriously. Here in my country (Spain) the recommended maximum level for office spaces is 45 dB(A) of equivalent continuous sound level (NBE-CA-88 regulation, only in Spanish: http://www.ual.es/Depar/proyectosingenieria/descargas/Normas_Edificacion/NBE-CA-88.pdf http://www.ual.es/Depar/proyectosingenieria/descargas/Normas...)
- tyingq 10y ago32 cores in one socket may also take a bite out of some servers that are currently 2 sockets.
- AnthonyMouse 10y ago> 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas This one will be interesting. The current Ryzen (like most of the Intel desktop range) has two channels, but everyone has been benchmarking it against the i7-6900K because they both have eight cores. The i7-6900K is the workstation LGA 2011 with four channels. If the workstation Ryzen will have eight channels...
- agumonkey 10y agoMy shallow understanding of big servers and IBM Z series amounted to "lots of dedicated IO processors". Seems like "mainstream" caught up with big blue.
- PeCaN 10y agoPretty much. Mainframes have been very I/O oriented from the start. Channel I/O (more or less DMA) with dedicated channel programs and processors can be very high-throughput.
- agumonkey 10y agoAlso I suppose it frees the logic processors from all IO (caching too?) related processing and allow for fancier strategies downstream .. (all guess fest)
- kev009 10y agoSort of. It ebbs and flows, generally more maintainable to do more in CPU/kernel and less in HW/firmware for PCs and of course price runs the market so there's a race to do less. Part of the mainframe price tag is getting long term support on the whole system stack, whereas PC vendors actively abandon stuff after a few years. That is a big risk for something like TCP offload engine. Every mainframe interface is basically an offload interface.. "computers" DMAing and processing to the CPs and each other. Every I/O device has a command processor, so it can handle channel errors and integrated pcie errors in a way PCs cannot. A PC with Chelsio NICs doing TCP offload with direct data placement or RDMA as well as Fiber Channel storage would be mini/mainframe-ish.
- gankedfrank 10y ago> x86 in 2017 Cool man... > SHA1 IN 2017 Uhhh, yeah, cool man
- yuhong 10y agoAs a side note, XOP had rotate instructions. Sadly it is no longer supported in Ryzen.
- kiddico 10y agoSorry, my google-fu isn't on point today; what's the difference between 1p and 1u. or 2p and 2u? My nomenclature knowledge is lacking ...
- throwawayish 10y agon-P / n-S / n-way = how many sockets/processors a system has. A 1S system has one socket / processor, a 2S system two, a 4S four and so on. x U (or x HE, if you're talking with a German manufacturer, they like to make that mistake ... ;) are rack-units, i.e. how large the case is.
- sp332 10y agoP = Processor and S = Socket (they're pretty interchangeable). U = rack Unit https://en.wikipedia.org/wiki/Rack_unit https://en.wikipedia.org/wiki/Rack_unit
- astrodust 10y agoThe title should be re-written to say "single and dual socket" not "1P and 2P".
- jug5 10y agoDoesn't matter when Naples launches, there will be no motherboards.
- daemonk 10y agoNice. This is the more interesting market for AMD rather than the gaming market in my opinion. 128 PCIe lanes and up to 4TB of ram will be awesome.
- ptrptr 10y agoGaming? More like consumer market, Ryzen 7 is definitely not suited for gamers, advertising it as such was IMO mistake. Nevertheless Naples can be big innovation in server segment. Also what with ECC? Ryzen can support it or not?
- alimbada 10y agoIt's just as suited for gaming as it is for anything else. The problem is everyone expected all games to run buttery smooth on day one with no hiccups. Ryzen specific game engine optimisations are coming according to AMD, as well as a Windows 10 scheduler patch. There are also other issues on the motherboard/BIOS side which manufacturers are working on.
- BuckRogers 10y agoYou can't say this enough to people, they just don't want to get it. New CPU arch, new platform, beta bios, new node, no OS scheduler patch, no engine optimizations. Considering all this, the performance is truly amazing.
- floatboth 10y agoNot being the top single-threaded performer which is required to push many many hundreds of frames per second != "not suited for gamers". Games in general are more likely to be GPU-bound!! Intel's quad cores are only really required for the pro Counter-Strike players who want 600fps at 1080p just to get the absolute latest frame. BTW they advertised it as good for gaming + streaming (h264 CPU encoding at the same time on the same machine). And "content creation", which pretty much always means video editing. IIRC Ryzen supports unbuffered ECC if the mainboard supports it.
- rl3 10y agoIn previous threads there was discussion about Intel processors, specifically Skylake (which is a desktop processor), being superior for server workloads involving vectorization. How will Naples fare on this front?
- quickben 10y agoThat front remains to be seen. However, 128 lanes, 8 channel ram; It will make a mess out of Intel in the vm hosting arena. I'm glad I don't own any Intel stock atm :)
- greggyb 10y agoThe VM hosting arena is exactly where cloud providers play. A high core count, energy efficient CPU with IO out the wazoo? I'm happy I bought AMD stock over the summer (:
- astrodust 10y agoOutside of specialized workloads, not a lot of software is vectorized. Maybe your database server can take advantage, but your application server will probably not benefit one bit.
- Tuna-Fish 10y agoBadly, but it doesn't matter because it's still just a tiny portion of the market.
- wtallis 10y agoDesktop Skylake doesn't support AVX-512. Server Skylake will, when it ships. (The Xeon E3 v5 doesn't, because it's the same chip as desktop Skylake.)
- rl3 10y agoRemoved the incorrect information from my post. Thanks for the correction.
- sp332 10y ago
- andy_ppp 10y agoHow well does, say, Postgres scale on such hardware? Is anything more that 8 cores overkill or can we assume good linear increases in queries per second...
- brianwawok 10y agoThis is from 2012: http://rhaas.blogspot.com/2012/04/did-i-say-32-cores-how-about-64.html http://rhaas.blogspot.com/2012/04/did-i-say-32-cores-how-abo... My guess is the 1 socket options scales great. 2 sockets are are less than ideal, and you will not double the 1 socket performance.
- mozumder 10y agoI'd like to see this data on Postgres scaling updated, with more info on the write scaling as well. (the chart appears to be for SELECT queries only)
- brianwawok 10y agoThe other change is now a single select can use multiple cores, so you could see how that scaled to 32, 64, 128 cores...
- qaq 10y agoOn highly concurrent PG systems by when using parallel queries you are sacrificing throughput for better latency. You really don't want to use more than a fairly small number of workers per single select.
- qaq 10y agoOutside of some very exotic scenarios you are IOPS bound on writes and not CPU bound.
- mozumder 10y agoIs that still a problem with cheap NVMe drives that can do 500k IOPS?
- drewg123 10y agoThe important thing here, from my perspective, is how NUMA-ish a single socket configuration will be. According to the article, a single package is actually made up of 4 dies, each with its own memory (and presumably cache hierarchy, etc). While trivially parallelizable workloads (like HPC benchmarks) scale quite well regardless of system topology, not all workloads do so. And teaching kernel schedulers about 2 levels of numa affinity may not be trivial. With that say, I'm looking forward to these systems.
- wtallis 10y agoIntel's largest CPUs are already explicitly NUMA on a single socket. They call it Cluster On Die: http://images.anandtech.com/doci/10401/03%20-%20Architectural%20Overview-page-037.jpg http://images.anandtech.com/doci/10401/03%20-%20Architectura...
- drewg123 10y agoVery true, I should have mentioned that. At least for us, COD doesn't seem to impact our performance at all, while NUMA does. I'm hoping that Naples is the same for us. However, there is an important difference. AMD seems to be putting multiple dies into the same package, whereas Intel seems to have (as the Cluster on Die name implies) everything on the same die. So my fear is that the interconnect between dies may not be fast enough to paper-over our NUMA weaknesses.
- p1esk 10y agoSounds like your application is latency sensitive, and not bandwidth sensitive, take a look at the graphs towards the end of this article: https://www.starwindsoftware.com/blog/numa-and-cluster-on-die https://www.starwindsoftware.com/blog/numa-and-cluster-on-di... There's not much difference in memory bandwidth between crossing domains on the same die (COD) vs crossing domains system wide (accessing memory for a different socket). What kind of computation are you running?
- 10y ago
- keth 10y agoI'm looking forward to the benchmarks since the performance per watt of the desktop parts (Ryzen R7) seems to be really good. Quite curious how it will compare against Skylake-EP. A quote from a anandtech forum post [0] reads promising: "850 points in Cinebench 15 at 30W is quite telling. Or not telling, but absolutely massive. Zeppelin can reach absolutely monstrous and unseen levels of efficiency, as long as it operates within its ideal frequency range." A comparison against a Xeon D at 30W would be interesting. The possibility of this monster maybe coming out sometime in the future is also quite nice: http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf http://www.computermachines.org/joe/publications/pdfs/hpca20... [0] https://forums.anandtech.com/threads/ryzen-strictly-technical.2500572/ https://forums.anandtech.com/threads/ryzen-strictly-technica...
- mtgx 10y agoIf they have a much better performance/$ than Intel, which they likely will have, it sounds like a good opportunity for AWS to significantly undercut Microsoft and Google (which recently bragged about purchasing expensive Skylake-E chips).
- chx 10y agoThere's opportunity cost to consider. Google has Skylake-E now which is not even available at retail yet.
- mtgx 10y agoWell, it also seems that Intel prioritized its customers. If I were Amazon or Microsoft (the rumors said Google and Facebook were the priority customers), I would get Naples just to spite Intel (it doesn't hurt that AMD's Naples likely offers better perf/$, too, though): https://semiaccurate.com/2016/11/17/intel-preferentially-offers-two-customers-skylake-xeon-cpus/ https://semiaccurate.com/2016/11/17/intel-preferentially-off...
- bit_logic 10y agoReally dumb move by Intel, this what happens when a company becomes too arrogant. They knew about Zen but probably just laughed it off as nothing. At the high level business decisions, things like this matter just as much as technical details like performance/$. Hard to believe they were dumb enough to piss off Amazon AWS, MS Azure, and others.
- deleted 10y ago[deleted]
- arca_vorago 10y agoThis is what I have really been looking forward to. I theorycrafted a more ideal system for the genetics work a former employer was doing, but didn't get to build it until after I had left there. A quad 16 core opteron system for a total of 64 cores (for physics calculations in comsol). I think that there is more potential use for high actual core count servers than many people realize, so I can't wait to build one. (for my purposes these days is as an game server in a colo, one of my projects is a multiplayer UE4 game) At the previous job where I built the 64-core system, I even emailed the AMD marketing department to see if we could do some PR campaign together, but I think it was too soon before the Naples drop, because I never got a response. Here's to hoping supermicro does a 4 cpu board for this... 124 cores would be amazing. (But I'll take 64 naples cores as long as it gets rid of the bugs and issues I found with the opterons).
- deepnotderp 10y agoOut of curiosity, I thought that genetics was the domain of gpus?
- CreRecombinase 10y agoIt's quite rare to find GPUs being used in genetics.
- moh_maya 10y ago//OT:: Your user name: a fan of the cre-lox system, or the enzyme itself? Cool uid! In my past life, I've used flp/frt & cre/lox; and studied mismatch repair enzymes. And topoisomerases.. :)
- noir_lord 10y agoIs that because the workloads are fundamentally unsuitable for current GPU architectures or because no one has took a good stab at it yet? I know very little about computation genetics/biology but it sounds interesting.
- 10y ago
- Coding_Cat 10y agoWith how big these chips are getting, I wonder if the next iteration will have an HBM last-level cache on chip.
- throwawayish 10y ago"IBM did it first" Well not with HBM (which is DRAM), but huge amounts of L3 SRAM on a MCM... POWER5 I believe.
- phkahler 10y agoThat's the old EHP concept. http://wccftech.com/amd-exascale-heterogeneous-processor-ehp-apu-32-zen-cores-hbm2/ http://wccftech.com/amd-exascale-heterogeneous-processor-ehp... I'd like to have that in the old project quantum package: http://wccftech.com/amd-project-quantum-not-dead-zen-cpu-vega-gpu/ http://wccftech.com/amd-project-quantum-not-dead-zen-cpu-veg... That would be a TFLOPS level supercomputer on your desk.
- keth 10y agoHere is the newest PDF about something like that: http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf http://www.computermachines.org/joe/publications/pdfs/hpca20...
- deepnotderp 10y agoI've long been advocating for a high i/o cpu with several pcie lanes. 128 lanes will support 8 GPUs at max bandwidth. AMD has positioned itself well.
- m3kw9 10y agoIn other words, we have a faster server chip coming
- Symmetry 10y agoSemi-ironically this looks like just the thing to use in a supercomputer controlling a good number of NVidia GPUs.
- PeCaN 10y agoWhat would be really interesting if AMD CPUs and GPUs both support their Infinity Fabric concept. Heterogeneous systems with high-performance direct memory access is a huge deal.
- gbrown_ 10y agoWas thinking the same thing. Like the CPU marked it's good to have competition with GPUs but it would be interesting if Nvidia picked up/ partnered with AMD. Oh well let's see how OpenPOWER pans out.
- HippoBaro 10y agoI think Naples will be a very serious threat to Intel in the server market. As Ryzen benchmarks & reviews have shown, Zen really shines in heavy-multithreaded applications. The typical workload of a server. Though I am kind of worried concerning memory access. Latency penalties when accessing non-local memory are very high on Zen CPUs due to the multi-die architecture design. Does that mean we will finally see some serious interest in Shared-Nothing design and alike in the future ?
- __mp 10y agoI'm wondering how they will stack up against XeonPhi.
- Demcox 10y agoJust having one of those in a workstation get me all warm and fuzzy.
- ajaimk 10y agoThis is the first I'm reading about the 32 cores being 4 dies on a package - Not sure how well that will work out in practice. IBM does something similar with Power servers where 2 dies on a package are used for lower end chips. Basically, using multiple dies increases latency significantly between the cores on different dies. This will affect performance. I will not judge till I see the benchmark though :-)
- emcrazyone 10y agocan anyone chime in as to why use PCIe over something more core to core direct? As I understand it, the CPU still needs to talk to a PCIe host/bridge controller. Why not have something that is more direct between processors?
- sliken 10y agoHypertransport is an AMD technology that's high bandwidth per line, low latency, and scalable. It's also cache-coherent (well there's a version that is), so it's great for connecting CPUs. But the AMD hardware is flexible and can use the same pins for either. So the single socket systems can have more pci-e lanes available, but the dual socket has less per socket because some of those lanes are used for hypertransport. What I can't figure out is why Intel and AMD aren't using similar (Hypertransport for AMD and QPI for intel) to connect directly to GPUs in a cache coherent way. These days the faster interconnects spend a decent fraction of their latency just getting across the PCI-e bus twice. So 100 Gbit networks, Infiniband, GPUs, etc all could take advantage of a lower latency cache coherent interface, but it's not available. I suspect mainly because qpi and hypertransport are incompatible and pci-e is good enough for the high volume cases.
- jabl 10y agoWell, AMD is one of the founding members of OpenCAPI, http://opencapi.org/ http://opencapi.org/ , so I guess there's some hope. It seems they haven't talked about it wrt Zen/Naples, maybe some later iteration will have it?
- ksec 10y ago1. Most of the benchmarks are not even compiled or made with Zen Optimization in mind. But the results are already promising, or even Surprising. 2. Compared to Desktop / Windows Ecosystem, their are much more Open Source Software on the Server side, along with usual Open Source Compiler. Which means any AMD Zen optimization will be far easier to deploy compared to Games and App on Desktop coded and compiled with Intel / ICC. 3. The sweet spot for Server Memory is still at 16GB DIMMs. A 256GB Memory for your caching needs or In-memory Database will now be much cheaper. 4. When are we going to get much cheaper 128GB DIMM Memory? Fitting 2TB Memory per Socket, and 4TB per U, along with 128 lanes for NVM-E SSD Storage, the definition of Big Data, just grown a little bigger. 5. Between now and 2020, the roadmap has Zen+ and 7nm. Along with PCI-E 4.0. I am very excited!
- keth 10y ago> 5. Between now and 2020, the roadmap has Zen+ and 7nm. Along with PCI-E 4.0. I am very excited! Yes, and it's rumored that the top end 7nm chip will be 48 cores (codename starship). Exciting times ahead now that the competition is back.
- galeos 10y agoThis is a multi-chip-module (MCM). Are the high core-count Xeons now all single die? Will be interesting to see what impact the MCM approach has on benchmarks as I supposed could have a latency impact in certain use cases?
- deelowe 10y agoThis is when things will get interesting. Ryzen appears to do better with hot and server workloads than gaming.
- deelowe 10y agoShould read HPC instead of "hot"
- hossbeast 10y agoHow feasible will a Naples desktop build be?
- rosege 10y agoLicensing Windows 2016 Datacenter would cost a fortune for the 2P server.