4 ms·
A link to the paper mentioned in the article (paywall/institution access): http://ieeexplore.ieee.org/document/7838397/ http://ieeexplore.ieee.org/document/7838
by Cyph0n 10y ago
A link to the paper mentioned in the article (paywall/institution access): http://ieeexplore.ieee.org/document/7838397/ http://ieeexplore.ieee.org/document/7838397/
TL;DR - Much lower erase time than NOR Flash (3 orders of magnitude), 1/3 voltage required for write/erase, all other parameters typically the same
The results from the paper are summarized as follows:
- Cell size is comparable to current NOR Flash (0.045 um^2)
- Endurance is also comparable (~10^5 cycles)
- Estimated 10 year retention @105C, compared to 150C for NOR
- Read time <25 ns, versus <10 ns
- Write time around 500 ns (1/2 of NOR)
- Erase time around 500 ns, compared with 10^6 ns for NOR (!)
- Energy consumption not yet measured, but claimed less than Flash
- Max voltage of 4.5V, versus 12V for Flash
- AstralStorm 10y agoThey didn't tell one thing: how long can it sustain data unpowered at what BER?
- mkj 10y agoThanks for the summary. With the same endurance but much lower erase time you could run out of write cycles in the blink of an eye?
- petra 10y agoYou forgot the most important stuff: it scales well with various technology nodes and processes, requires much less mask layers than flash and it is much more cost effective. Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current!
- RandomOpinion 10y ago>Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current! Um, no, that's not the point of the NC FET. The "negative capacitance" aspect of the ferroelectric material means that the NC FET can switch on or off faster, reducing power wasted in the switching process, and therefore allow chips to run cooler. See https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-power.html https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-... for a general explanation or https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-171.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-... for a technical explanation.
- petra 10y agoIn [1] , they build a non-volatile flip-flop out of a ncfet. [1]section 5.3 , https://www.google.co.il/url?sa=t&source=web&rct=j&url=http://nics.ee.tsinghua.edu.cn/people/lixq/resources/SRC_TechCON2015-NCFET.pdf&ved=0ahUKEwi3jeK_tJbSAhVLAcAKHZbUCGEQFggvMAQ&usg=AFQjCNES_qLrdDN0XglEDFQCb08emPU2aQ&sig2=-P1AEDalQHR3V8XsyPHXRA https://www.google.co.il/url?sa=t&source=web&rct=j&url=http:...
- runeks 10y agoWith regards to energy consumption, from the article: > FeFETs, according to FMC, provide fast switching at low power. FMC says it provides a 1,000X improvement in per-bit write energy.
- amelius 10y agoWhat is the difference between writing and erasing here?
- Maakuth 10y agoYou can only write once to every block, then you have to erase it completely before reusing. This causes so-called write amplification, in the extreme meaning that changing one bit requires erasure and rewrite for the whole 4K block. See here for deeper explanation: https://www.extremetech.com/extreme/210492-extremetech-explains-how-do-ssds-work https://www.extremetech.com/extreme/210492-extremetech-expla... edit: Typically the SSD has a pool of empty blocks, so in actuality, rewrite is done to one of these blocks and the previously used block is erased and returned to the pool.
- amelius 10y agoThanks! > Typically the SSD has a pool of empty blocks So erase time (the main advantage of this new FeFET technology) does not matter much in practice?
- Maakuth 10y agoMy guess is that it should help with performance on full SSD drives and when there's a lot of small writes that burn through the pooled erased blocks.
- pjc50 10y agoI think it does; while theoretically the storage driver should maintain adequate empty blocks, often they don't - see reports of "SSD performance degradation".
- mrob 10y agoFeFETs are planned for embedded non-volatile memory, eg. the memory for code storage build into microcontrollers, not SSDs. In current devices this is typically NOR flash, and the code executes directly from it. There's no pool of empty blocks, but the cells are single level so endurance is still acceptable.