5 ms·

FeFETs: How this new memory stacks up against existing non-volatile memory

94 points by SemiTom 10y ago

sverige 10y ago
This stuff is fascinating, especially the challenges in fabrication as the theoretical limits are approached. I do have a question, if an expert could help explain. The article says, "With FMC’s proprietary hafnium oxide, the standard gate dielectric can be made ferroelectric—even for film thicknesses that compare to the one used in standard logic transistors. This proprietary hafnium oxide integrates extremely well with all current and future processes utilizing HKMG. Therefore, a scalable ferroelectric FET finally becomes possible." What is proprietary about the hafnium oxide? Is it the process of creating it, or the molecule itself?
- Cyph0n 10y ago
  Hafnium oxide itself doesn't seem to be proprietary, and neither does the process of producing thin films that have ferroelectric properties[1]. My guess is that they've made some additional modifications to the compound and/or process. I'm venturing way outside of my field here, so I could be completely wrong. [1]: http://aip.scitation.org/doi/abs/10.1063/1.3634052 http://aip.scitation.org/doi/abs/10.1063/1.3634052 (search for the title in Google Scholar to get a PDF)
- RandomOpinion 10y ago
  If I understand it correctly, it is the process of depositing the HfO2 onto the wafer in a way that it retains its ferroelectric properties and is compatible with other chipmaking processes that is proprietary. Depositing it improperly would result in defects at the junction between the HfO2 and the underlying gate that would render the FeFET nonfunctional.
  - sevensor 10y ago
    When I was in semiconductor manufacturing, we tried using a hafnium oxide layer in the capacitor dielectric for our DRAM. It did not go well, if I recall correctly (10 years back). Not for design reasons -- we were using it for its dielectric properties, not its ferromagnetic ones -- but for process reasons. It was hell on the diffusion furnaces. Flakes everywhere, wafers sticking. Lots of angry morning meetings.
- SemiTom 10y ago
  A bit about Hafnium Oxide http://semiengineering.com/many-paths-to-hafnium-oxide/ http://semiengineering.com/many-paths-to-hafnium-oxide/
Cyph0n 10y ago
A link to the paper mentioned in the article (paywall/institution access): http://ieeexplore.ieee.org/document/7838397/ http://ieeexplore.ieee.org/document/7838397/ TL;DR - Much lower erase time than NOR Flash (3 orders of magnitude), 1/3 voltage required for write/erase, all other parameters typically the same The results from the paper are summarized as follows: - Cell size is comparable to current NOR Flash (0.045 um^2) - Endurance is also comparable (~10^5 cycles) - Estimated 10 year retention @105C, compared to 150C for NOR - Read time <25 ns, versus <10 ns - Write time around 500 ns (1/2 of NOR) - Erase time around 500 ns, compared with 10^6 ns for NOR (!) - Energy consumption not yet measured, but claimed less than Flash - Max voltage of 4.5V, versus 12V for Flash
- AstralStorm 10y ago
  They didn't tell one thing: how long can it sustain data unpowered at what BER?
- mkj 10y ago
  Thanks for the summary. With the same endurance but much lower erase time you could run out of write cycles in the blink of an eye?
- petra 10y ago
  You forgot the most important stuff: it scales well with various technology nodes and processes, requires much less mask layers than flash and it is much more cost effective. Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current!
  - RandomOpinion 10y ago
    >Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current! Um, no, that's not the point of the NC FET. The "negative capacitance" aspect of the ferroelectric material means that the NC FET can switch on or off faster, reducing power wasted in the switching process, and therefore allow chips to run cooler. See https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-power.html https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-... for a general explanation or https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-171.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-... for a technical explanation.
pjc50 10y ago
Sounds like an improvement over FRAM, which is already a shipping product that you can buy today - albeit more expensive than Flash and not as dense. The ability to build with standard HKMG (high-k metal gate) wafer processing (unlike Flash) is very handy - means FeFET memory can be incorporated into high-speed microcontrollers.
acqq 10y ago
"First and foremost, FMC is aiming at the embedded NVM space." It also seems that they compare it with NOR and not with NAND, which again points to the scenarios where not much is stored and not often rewritten. Then it's not a technology for SSD's or USB sticks, how I understand it, but it's to allow to have a single chip which has both the logic and the re-writable firmware. And they claim it's cheaper to achieve that than with the competing technologies.

94 points by SemiTom 10y ago

This stuff is fascinating, especially the challenges in fabrication as the theoretical limits are approached. I do have a question, if an expert could help explain. The article says, "With FMC’s proprietary hafnium oxide, the standard gate dielectric can be made ferroelectric—even for film thicknesses that compare to the one used in standard logic transistors. This proprietary hafnium oxide integrates extremely well with all current and future processes utilizing HKMG. Therefore, a scalable ferroelectric FET finally becomes possible." What is proprietary about the hafnium oxide? Is it the process of creating it, or the molecule itself?

Cyph0n 10y ago
Hafnium oxide itself doesn't seem to be proprietary, and neither does the process of producing thin films that have ferroelectric properties[1]. My guess is that they've made some additional modifications to the compound and/or process. I'm venturing way outside of my field here, so I could be completely wrong. [1]: http://aip.scitation.org/doi/abs/10.1063/1.3634052 http://aip.scitation.org/doi/abs/10.1063/1.3634052 (search for the title in Google Scholar to get a PDF)
RandomOpinion 10y ago
If I understand it correctly, it is the process of depositing the HfO2 onto the wafer in a way that it retains its ferroelectric properties and is compatible with other chipmaking processes that is proprietary. Depositing it improperly would result in defects at the junction between the HfO2 and the underlying gate that would render the FeFET nonfunctional.
- sevensor 10y ago
  When I was in semiconductor manufacturing, we tried using a hafnium oxide layer in the capacitor dielectric for our DRAM. It did not go well, if I recall correctly (10 years back). Not for design reasons -- we were using it for its dielectric properties, not its ferromagnetic ones -- but for process reasons. It was hell on the diffusion furnaces. Flakes everywhere, wafers sticking. Lots of angry morning meetings.
SemiTom 10y ago
A bit about Hafnium Oxide http://semiengineering.com/many-paths-to-hafnium-oxide/ http://semiengineering.com/many-paths-to-hafnium-oxide/

Cyph0n 10y ago

A link to the paper mentioned in the article (paywall/institution access): http://ieeexplore.ieee.org/document/7838397/ http://ieeexplore.ieee.org/document/7838397/ TL;DR - Much lower erase time than NOR Flash (3 orders of magnitude), 1/3 voltage required for write/erase, all other parameters typically the same The results from the paper are summarized as follows: - Cell size is comparable to current NOR Flash (0.045 um^2) - Endurance is also comparable (~10^5 cycles) - Estimated 10 year retention @105C, compared to 150C for NOR - Read time <25 ns, versus <10 ns - Write time around 500 ns (1/2 of NOR) - Erase time around 500 ns, compared with 10^6 ns for NOR (!) - Energy consumption not yet measured, but claimed less than Flash - Max voltage of 4.5V, versus 12V for Flash

AstralStorm 10y ago
They didn't tell one thing: how long can it sustain data unpowered at what BER?
mkj 10y ago
Thanks for the summary. With the same endurance but much lower erase time you could run out of write cycles in the blink of an eye?
petra 10y ago
You forgot the most important stuff: it scales well with various technology nodes and processes, requires much less mask layers than flash and it is much more cost effective. Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current!
- RandomOpinion 10y ago
  >Edit:also , they mentioned an ncfet transistor for general use.since this transistor remember his state, you may not have to power it in sleep mode(whole circuit or partial), and thus could get zero leakage current! Um, no, that's not the point of the NC FET. The "negative capacitance" aspect of the ferroelectric material means that the NC FET can switch on or off faster, reducing power wasted in the switching process, and therefore allow chips to run cooler. See https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-power.html https://phys.org/news/2011-09-ferroelectrics-pave-ultra-low-... for a general explanation or https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-171.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-... for a technical explanation.

pjc50 10y ago

Sounds like an improvement over FRAM, which is already a shipping product that you can buy today - albeit more expensive than Flash and not as dense. The ability to build with standard HKMG (high-k metal gate) wafer processing (unlike Flash) is very handy - means FeFET memory can be incorporated into high-speed microcontrollers.

acqq 10y ago

"First and foremost, FMC is aiming at the embedded NVM space." It also seems that they compare it with NOR and not with NAND, which again points to the scenarios where not much is stored and not often rewritten. Then it's not a technology for SSD's or USB sticks, how I understand it, but it's to allow to have a single chip which has both the logic and the re-writable firmware. And they claim it's cheaper to achieve that than with the competing technologies.