3 ms·
The MSP430x5xx and MSP430x6xx families have this problem. From the user-guide [1]: > Include at least one instruction between the clear of an interrupt enable
by jlubawy 10y ago
The MSP430x5xx and MSP430x6xx families have this problem. From the user-guide [1]:
> Include at least one instruction between the clear of an interrupt enable or interrupt flag and the EINT instruction. For example: Insert a NOP instruction in
front of the EINT instruction.
> Include at least one instruction between DINT and the start of an code
sequence that requires protection from interrupts. For example: Insert a NOP
instruction after the DINT
Luckily if you use the MSP compiler's intrinsic functions to enable/disable interrupts it takes care of this for you.
[1] http://www.ti.com/lit/pdf/slau208 http://www.ti.com/lit/pdf/slau208
- dfox 10y agoWhat I described happened on G2553 with USCI_A in SPI mode. Given the fact that various code samples on the net do not handle this behavior it seems that it is either happening only for some configurations or only on some versions of the HW. But: when you see even bytes on SPI dropped or replaced with previous ones, add NOP.