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Free Range VHDL – VHDL programming book available for free
- notforgot 10y agoCan I write an ASIC with it?
- emddudley 10y agoNo, because VHDL is used for configuring FPGAs. An ASIC is a different beast entirely.
- sofayam 10y agoActually yes - the H stands for hardware: that's any kind of digital logic. You just need a different "back end" and then in theory the same model can run on various targets - in fact there is a whole business model around getting a design up and running on an FPGA and then porting it to an ASIC once you can justify the volume.
- aurelian15 10y agoYou can most certainly build ASICs in VHDL. VHDL is not restricted to any target technology. There are (commercial) tools which allow you to synthesise the masks needed for ASIC production from RTL (register transfer level) VHDL code given a cell library for your target technology. See random Google search result [1]. [1] http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/essential_vhdl_pdfs/essential_vhdl0-23.pdf http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lecture...
- kbumsik 10y agoNo it is not entirely different. Don't forget that FPGA is originally made for prototyping an ASIC, and HDL came out to configure digital circuit before FPGA is invented. Of course an ASIC cannot be made with only HDL, and not sure if it is a correct expression to say 'to write' an ASIC.
- ajdlinux 10y agoVHDL and Verilog are used in pretty much all CPU design.
- bostand 10y agoYes you can! (no idea why emddudley is claiming otherwise)
- anfractuosity 10y agoI was under the impression you could too. Can you somehow convert it to a format say Magic VLSI could open, out of curiosity.
- analognoise 10y agoMagic is a layout tool - you need to synthesize your HDL (Verilog and/or VHDL), then map it to the technology you are trying to target. In short, not directly - it's the front end tool, and Magic is a different front end tool (direct, full custom layout).
- kbumsik 10y agoYou can design an ASIC with HDL before it is produced but ASIC is not programmable. An ASIC is produced as it is. So you CAN'T WRITE an ASIC.
- blacksmythe 10y agoSee Introduction to ASIC Design for a detailed description: https://www.u-cursos.cl/ingenieria/2010/2/EL653/1/material_docente/bajar?id_material=305352
- dang 10y agoDiscussed in 2012: https://news.ycombinator.com/item?id=3580537 https://news.ycombinator.com/item?id=3580537.
- oelang 10y agoWe're 2017, VHDL 2008 was released 9 years ago, and this book is using VHDL 93.
- metaphor 10y agoAs the old hardware commandment goes: if it ain't broke, don't fix it?
- jevinskie 10y agoIt VHDL as implemented at the time was broken, at least as of 2010. [0] VHDL 2008 support would have definitely had a positive impact on the VHDL source code (making it smaller and more comprehensible). There were so many 2008 features I wished to use but simply couldn't. With the slow pace that FPGA toolchains progress, I'd imagine the situation isn't vastly better today. Luckily I read [1] and realized that VHDL can be written in a better way, even with old toolchains. This 2proc style is so much easier to debug than typical RTL syle. It was unfortunate that the 2010 era Quartus II toolchain did not optimize my behavioral code well. The CPU caches were the worst offenders, which isn't too surprising. Tons of enormous, almost certainly inefficient, muxes really pushed the LE limits on the FPGA and my patience during the very long synthesis time. [0]: https://github.com/jevinskie/mips--/tree/master/project4/source https://github.com/jevinskie/mips--/tree/master/project4/sou... [1]: http://www.gaisler.com/doc/vhdl2proc.pdf http://www.gaisler.com/doc/vhdl2proc.pdf
- EvgeniyZh 10y agoYou can always contribute, the link to github is provided in one of the comments.
- zump 10y agoPlease don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).
- pjmlp 10y agoI rather use Ada like syntax.
- EvgeniyZh 10y agoAny good Verilog/SystemVerilog book you can recommend?
- blackguardx 10y agohttp://www.doe.carleton.ca/~jknight/97.478/97.478_02F/PetervrlQ.pdf http://www.doe.carleton.ca/~jknight/97.478/97.478_02F/Peterv... I do FPGA design as part of my job. This is the most concise document I've found that covers everything you need to know to get started. Many verilog books just focus on the language. This short pdf focuses on how to use the language to do hardware design, which is what most people actually want to learn.
- BillBohan 10y agoMany thanks for that link. I wrote VHDL for 10 years and sometimes had to interface to Verilog modules. I only know enough Verilog to read it and get a rough idea of what it does, sometimes asking for help from an expert.
- analognoise 10y agoThis is not a good reason not to use VHDL- GHDL is open source and simulates VHDL? Verilator is only useful if you don't need backannotated timing constraints.
- q3k 10y agoWhile I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be redefining the same signal bundles over and over and over again). But yes, Verilator is quite nice. I think both Verilog and VHDL are fairly terrible and are unnecessarily stuck at the connecting-wires-together paradigm. I have high hopes for systems like Clash[1]/Chisel[2]/SpinalHDL[3] to gain more widespread usage and finally make higher abstraction levels and metaprogramming standard in the industry. [1] - http://www.clash-lang.org/ http://www.clash-lang.org/ [2] - https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ [3] - https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL
- AlexanderDhoore 10y agoI learned VHDL a few months ago. Since then I've build a few projects with it (some PCIe and ethernet stuff). I was very excited to learn a HDL because FPGAs seem like extremely powerful devices. However, I now know why FPGAs aren't as popular as they could be: the tools are horrible. There is no way FPGAs will become popular among software developers unless the tooling improves dramatically. You can really tell that it was all build by hardware engineers who know their electronics very well, but not good software design.
- anfractuosity 10y agoCool! I'm going to attempt to learn VHDL, as I just picked up a Zybo board to learn with. I'm just wondering what you used for PCIe out of interest? A while ago I picked up an Igloo2 board, but found their software impossible to use under Linux alas.
- AlexanderDhoore 10y agoI've been working with a NetFPGA 10G board. It's quite cheap for academic research, but not for hobbyists. It's also rather old now. The project comes with open source HDL, but I've had immense trouble getting it to work. You need a special license from Xilinx just to get started (ethernet core). I wish I had chosen something else. I tried a Lattice ECP5 Versa board, but you need to sign a NDA just to get the ethernet documentation, which of course is impossible.
- metaphor 10y ago> There is no way FPGAs will become popular among software developers unless the tooling improves dramatically. Care to expound in what way? I don't disagree with your opinion completely, but I suspect our reasons differ. IMHO, the barrier isn't so much the tools, but a clashing of paradigms. All too often, traditional software developers without a solid foundational background in digital hardware architectures think they can easily pick up a HDL as if it were yet another programming language. The HD part is quickly forgotten as behavioral processes are hacked away using all too familiar constructs like if-then-else, for/while loops, etc. Inference warnings are ignored, timing constraints are shrugged off, metastability and synchronization aren't even a thing, let alone driver/receiver selection, pinmap planning, and signal integrity considerations at the PCB level...set to default and things should just work, right? Anecdotally speaking, the only thing in common that HDLs have with traditional programming languages is a superficial charset. I think every software developer who has ever used tools like VS, Eclipse, Emacs, Vim, Make, Doxygen, Git, etc. would agree that each has its quirks and it takes a bit of use before a comfortable flow is discovered. FPGA vendor tools are no different, except--testbed simulations aside--there's that immutably distinct custom hardware integration end-game that most traditional software has the pleasure of conveniently abstracting away. Any kernel/driver developers with HDL proficiency care to chime in? P.S. ground-up PCIe/Ethernet FSM+datapath architectures after a few months without prior HDL experience is really impressive.
- cyphar 10y agoQuite a few people have been working on making VHDL more accessible by generating it all from Python. Tim Ansell gave a talk about it at LCA 2017 (https://www.youtube.com/watch?v=MkVX_mh5dOU https://www.youtube.com/watch?v=MkVX_mh5dOU), and it seems pretty cool.
- gluggymug 10y agoNo way to specify different clocks or resets from what I can see. That's a massive limitation to your designs.