5 ms·

Are you saying this one isn't correct? Confused what point you're trying to make.

vvanders 10y ago
The atomic compare and swap is only one part of getting it right. You also have to deal with memory and instruction fences. Certain architectures have different semantics when it comes to that ordering so something that works on x86 for instance might explode on PPC or ARM. If you want to verify that the algorithms are correct you basically have to do static analysis and the only way you'll do that is if you have access to the microcode and register models(I.E. you make CPUs). [edit] To put this into practical terms I spent some time working with a popular game engine that used a lockfree queue at it's core rendering path. It wasn't until 2 or 3 titles had shipped on this engine that it was discovered that there was a bug in the lockfree algo. We're talking trillions of operations under many different threading and context switching loads and at least 3 different CPU architectures.
- jdright 10y ago
  Can you cite the name of the tech or any of the games?
- panic 10y ago
  How was the bug discovered? Sounds like a fun story.
- jjawssd 10y ago
  What was the solution?
  - vvanders 10y ago
    More fences :) (and the overhead that came with them)
- trungaczne 10y ago
  I don't get the point you're trying to make. Aren't std::memory_order's guarantees supposed to work with all support archs? The code in the OP does use memory fences. Are you implying that their implementation are incorrect?
  - vvanders 10y ago
    I'm not implying their implementation is incorrect. Just that these types of things are very easy to get wrong and when you do it's usually the type of bugs that take months to track down after you've eliminated every other subsystem involved. Generally if there's not a huge organization putting their reputation(and $$$) on the line there is going to be bugs. Most of the time if you're going lockfree for performance reasons there's usually much large gains to be found in your cache usage or overall architecture.
    - sillysaurus3 10y ago
      Generally if there's not a huge organization putting their reputation(and $$$) on the line there is going to be bugs. This argument applies to any hard problem, so it doesn't seem valid. Whether there's an important bug in a project depends on someone's skill and on how much time they've dedicated to it, and it's hard to know how skilled or dedicated someone is.
      - je42 10y ago
        this is less about "skill" but about the awareness how the different CPUs are implemented and where the algorithm is not behaving correctly in conjunction with the CPU spec. In addition the error class is a mean one: doesn't happen often statistically and difficult to reproduce and as such can be very expensive to track down.
        sillysaurus3 10y ago
        The specs are quite clear about memory fences. Just because something has a failure mode that's hard to detect doesn't mean that luck has anything to do with implementing it correctly. And if luck isn't a factor, then that leaves skill and dedication.
- TeMPOraL 10y ago
  Assuming I don't have access to CPU specs, how could I debug constructs like this queue? Should I set aside a machine and have it pound the queue with random data for the next six months, alerting me each time the error rate rises above cosmic ray threshold?
  - vvanders 10y ago
    > a machine In the absence of formal proof think 50+ machines. You basically setup a lab to run 24/7 and a/b with a hope that you repro. Same technique works for really gnarly intermittent driver bugs. It's still no guarantee but at least you get in the same range assuming the execution profile is diverse and robust.

The atomic compare and swap is only one part of getting it right. You also have to deal with memory and instruction fences. Certain architectures have different semantics when it comes to that ordering so something that works on x86 for instance might explode on PPC or ARM. If you want to verify that the algorithms are correct you basically have to do static analysis and the only way you'll do that is if you have access to the microcode and register models(I.E. you make CPUs). [edit] To put this into practical terms I spent some time working with a popular game engine that used a lockfree queue at it's core rendering path. It wasn't until 2 or 3 titles had shipped on this engine that it was discovered that there was a bug in the lockfree algo. We're talking trillions of operations under many different threading and context switching loads and at least 3 different CPU architectures.

jdright 10y ago
Can you cite the name of the tech or any of the games?
panic 10y ago
How was the bug discovered? Sounds like a fun story.
jjawssd 10y ago
What was the solution?
- vvanders 10y ago
  More fences :) (and the overhead that came with them)
trungaczne 10y ago
I don't get the point you're trying to make. Aren't std::memory_order's guarantees supposed to work with all support archs? The code in the OP does use memory fences. Are you implying that their implementation are incorrect?
- vvanders 10y ago
  I'm not implying their implementation is incorrect. Just that these types of things are very easy to get wrong and when you do it's usually the type of bugs that take months to track down after you've eliminated every other subsystem involved. Generally if there's not a huge organization putting their reputation(and $$$) on the line there is going to be bugs. Most of the time if you're going lockfree for performance reasons there's usually much large gains to be found in your cache usage or overall architecture.
  - sillysaurus3 10y ago
    Generally if there's not a huge organization putting their reputation(and $$$) on the line there is going to be bugs. This argument applies to any hard problem, so it doesn't seem valid. Whether there's an important bug in a project depends on someone's skill and on how much time they've dedicated to it, and it's hard to know how skilled or dedicated someone is.
    - je42 10y ago
      this is less about "skill" but about the awareness how the different CPUs are implemented and where the algorithm is not behaving correctly in conjunction with the CPU spec. In addition the error class is a mean one: doesn't happen often statistically and difficult to reproduce and as such can be very expensive to track down.
      - sillysaurus3 10y ago
        The specs are quite clear about memory fences. Just because something has a failure mode that's hard to detect doesn't mean that luck has anything to do with implementing it correctly. And if luck isn't a factor, then that leaves skill and dedication.
TeMPOraL 10y ago
Assuming I don't have access to CPU specs, how could I debug constructs like this queue? Should I set aside a machine and have it pound the queue with random data for the next six months, alerting me each time the error rate rises above cosmic ray threshold?
- vvanders 10y ago
  > a machine In the absence of formal proof think 50+ machines. You basically setup a lab to run 24/7 and a/b with a hope that you repro. Same technique works for really gnarly intermittent driver bugs. It's still no guarantee but at least you get in the same range assuming the execution profile is diverse and robust.