3 ms·

So does it have a MMU? That would make it even more superior to Arduino boards.

mwcampbell 10y ago
It seems to me that an MMU is no good if the board doesn't have enough RAM to run a general-purpose operating system, as opposed to a bare-metal program or a real-time OS like a microcontroller usually uses.
- wolfgke 10y ago
  > It seems to me that an MMU is no good if the board doesn't have enough RAM to run a general-purpose operating system, as opposed to a bare-metal program or a real-time OS like a microcontroller usually uses. For a realtime operating system at least a Memory Protection Unit (to use the word that ARM introduced for this limited form of an MMU) is very useful since it can easily make the OS much more reliable if a process cannot write to memory adresses of the kernel or other processes. EDIT: Or is such an MPU implied by the support for "Privileged ISA Specification v1.9.1"?
  - pjmlp 10y ago
    > is very useful since it can easily make the OS much more reliable if a process cannot write to memory adresses of the kernel or other processes. If you make use of memory safe systems programming languages on bare metal, like Ada, SPARK, Rust, Oberon-07 than it isn't usually an issue, since the unsafe code will be quite constrained. For example, http://www.astrobe.com/boards.htm http://www.astrobe.com/boards.htm
56245623456 10y ago
The website says it is conforming to "RISC-V Privileged ISA Specification, Version 1.9.1" which seems to specify a paging mechanism. I didn't read all of it though, so I may have overlooked an "optional" or something.
- rwmj 10y ago
  The most basic option for RISC-V is base + bound in M-mode which isn't paging and can barely be described as an "MMU". (Of course RISC-V also supports much more advanced options)
mwachs5 10y ago
The RISC-V ISA defines different privilege levels: Machine, Hypervisor, Supervisor, User. It is possible for a chip to conform to the RISC-V Privilege Spec v1.9 by only implementing the bare metal or Machine mode, which is what the chip on this board does. So the chip on this board does not have User mode or an MMU.

It seems to me that an MMU is no good if the board doesn't have enough RAM to run a general-purpose operating system, as opposed to a bare-metal program or a real-time OS like a microcontroller usually uses.

wolfgke 10y ago
> It seems to me that an MMU is no good if the board doesn't have enough RAM to run a general-purpose operating system, as opposed to a bare-metal program or a real-time OS like a microcontroller usually uses. For a realtime operating system at least a Memory Protection Unit (to use the word that ARM introduced for this limited form of an MMU) is very useful since it can easily make the OS much more reliable if a process cannot write to memory adresses of the kernel or other processes. EDIT: Or is such an MPU implied by the support for "Privileged ISA Specification v1.9.1"?
- pjmlp 10y ago
  > is very useful since it can easily make the OS much more reliable if a process cannot write to memory adresses of the kernel or other processes. If you make use of memory safe systems programming languages on bare metal, like Ada, SPARK, Rust, Oberon-07 than it isn't usually an issue, since the unsafe code will be quite constrained. For example, http://www.astrobe.com/boards.htm http://www.astrobe.com/boards.htm

56245623456 10y ago

The website says it is conforming to "RISC-V Privileged ISA Specification, Version 1.9.1" which seems to specify a paging mechanism. I didn't read all of it though, so I may have overlooked an "optional" or something.

rwmj 10y ago
The most basic option for RISC-V is base + bound in M-mode which isn't paging and can barely be described as an "MMU". (Of course RISC-V also supports much more advanced options)

mwachs5 10y ago

The RISC-V ISA defines different privilege levels: Machine, Hypervisor, Supervisor, User. It is possible for a chip to conform to the RISC-V Privilege Spec v1.9 by only implementing the bare metal or Machine mode, which is what the chip on this board does. So the chip on this board does not have User mode or an MMU.