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If Chisel is lower level than SystemC or SystemVerilog, and those two have much more acceptance, why go with Chisel ? Aren't modern systems complex enough to ju

by petra 10y ago

If Chisel is lower level than SystemC or SystemVerilog, and those two have much more acceptance, why go with Chisel ? Aren't modern systems complex enough to justify abstraction ?

seldridge 10y ago
The author doesn't have this correct. Chisel is a domain specific language for hardware written in Scala that emits Verilog in Chisel2 or an intermediate representation of RTL (FRRITL) in Chisel3 which is then compiled in an LLVM-like fashion (passes that transform the FIRRTL) to Verilog. SystemVerilog has all sorts of nice object-oriented features, but you can't use any of them for synthesizable code as you're dependent on the tool vendors supporting useful, yet complex things (e.g., classes, inheritance). Chisel avoids this whole problem by giving you access to extremely useful programming features (e.g., classes, functional programming) while still maintaining compatibility with whatever your ASIC/FPGA toolflow is.
pjc50 10y ago
I don't think they do have much adoption. SystemVerilog is still Verilog, and most of the new functions are aimed at simulation and testbench use. SystemC is rather painful as you have to write an artificially constrained subset and style of C. > "Vendors pushing high-level synthesis have a decades long track record of overpromising and under-delivering." Abstraction is important, but in hardware detail matters. In software you can afford to have a less efficient language if it results in faster development. This is absolutely not true of hardware. High-level synthesis has usually held out misleading promises of portability; that you might be able to get some complex application working written by (cheaper, easier to hire) software developers, then just drop it straight onto a chip. That's simply not true because the constraints are different. Chisel looks extremely promising, as it addresses a lot of what I'd say were Verilog pain points: Algebraic construction and wiring Abstract data types and interfaces Bulk connections Hierarchical + object oriented + functional construction
- tonmoy 10y ago
  SystemVerilog does seem to be used more and more. It is just verilog from the designer's perspective, but you have less chance to make mistakes, easier to write and the synthesis tool has more control over how to optimize the design.
aninhumer 10y ago
Chisel has a lower level model, but since it's Scala, it's a much higher level language than SystemC or SystemVerilog. Sure you have to specify things at the gate level, but you have the power to build abstractions on top of that (and indeed most of the ones other HDLs would provide are already there).
trevortheblack 10y ago
Chisel is fantastic. And could for a large swath of hw development replace verilog. Hell, Verilog is loaded with problems. But companies won't adopt Chisel because the tools they have now just work. So Chisel is of academic interest, and little else.

by petra 10y ago

If Chisel is lower level than SystemC or SystemVerilog, and those two have much more acceptance, why go with Chisel ? Aren't modern systems complex enough to justify abstraction ?

seldridge 10y ago

The author doesn't have this correct. Chisel is a domain specific language for hardware written in Scala that emits Verilog in Chisel2 or an intermediate representation of RTL (FRRITL) in Chisel3 which is then compiled in an LLVM-like fashion (passes that transform the FIRRTL) to Verilog. SystemVerilog has all sorts of nice object-oriented features, but you can't use any of them for synthesizable code as you're dependent on the tool vendors supporting useful, yet complex things (e.g., classes, inheritance). Chisel avoids this whole problem by giving you access to extremely useful programming features (e.g., classes, functional programming) while still maintaining compatibility with whatever your ASIC/FPGA toolflow is.

pjc50 10y ago

I don't think they do have much adoption. SystemVerilog is still Verilog, and most of the new functions are aimed at simulation and testbench use. SystemC is rather painful as you have to write an artificially constrained subset and style of C. > "Vendors pushing high-level synthesis have a decades long track record of overpromising and under-delivering." Abstraction is important, but in hardware detail matters. In software you can afford to have a less efficient language if it results in faster development. This is absolutely not true of hardware. High-level synthesis has usually held out misleading promises of portability; that you might be able to get some complex application working written by (cheaper, easier to hire) software developers, then just drop it straight onto a chip. That's simply not true because the constraints are different. Chisel looks extremely promising, as it addresses a lot of what I'd say were Verilog pain points: Algebraic construction and wiring Abstract data types and interfaces Bulk connections Hierarchical + object oriented + functional construction

tonmoy 10y ago
SystemVerilog does seem to be used more and more. It is just verilog from the designer's perspective, but you have less chance to make mistakes, easier to write and the synthesis tool has more control over how to optimize the design.

aninhumer 10y ago

Chisel has a lower level model, but since it's Scala, it's a much higher level language than SystemC or SystemVerilog. Sure you have to specify things at the gate level, but you have the power to build abstractions on top of that (and indeed most of the ones other HDLs would provide are already there).

trevortheblack 10y ago

Chisel is fantastic. And could for a large swath of hw development replace verilog. Hell, Verilog is loaded with problems. But companies won't adopt Chisel because the tools they have now just work. So Chisel is of academic interest, and little else.