3 ms·

DDR4-SDRAM achieves speeds in excess of 1.2 GHz over distances of 4" or more. That doesn't leave too much wiggle room.

by creshal 10y ago

iheartmemcache 10y ago
Surprisingly, the behavior at that speeds is fairly well known. I don't even think you need to move from FR4 to a more controlled material (e.g.generally in mmWave, Isola FR408, along with sometimes Rogers stuff, IME, is what is used). Allegro PCB SI(Signal Integrity) even models high speed timing fairly well at the design stage. You've got plenty of stuff at the test stage too. E.g., the gear on high-end Lecroy's metrology test gear is at 100ghz. Agilent (Keysight, whatever, it's still HP to me) has a full test rig for USB3.1[0] at 10gbps for their consumer level gear (again, fairly slow). Step it up to FPGA speeds and here's[1] an app-note by Altera with way higher speeds. Here's a really brief overview of 'rules of thumb' that work up to PCI-e[2] by TI. 50 minutes and worth a watch. Clean power that won't couple in, matching lines lengths on diff pairs, proper isolated ground planes (give AGND and DGND their own layers) and proper termination will easily get you 95% of the way there. (Shameless promotion-- available for high-speed design, pre-EMC compliance testing, fault diagnostics, etc). [0] http://www.keysight.com/en/pd-2472798-pn-U7243B/usb-31-compliance-test-software-for-infiniium-oscilloscopes?pm=PL&nid=-32976.1106319&cc=US&lc=eng http://www.keysight.com/en/pd-2472798-pn-U7243B/usb-31-compl... [1] https://www.altera.com/en_US/pdfs/literature/an/an528.pdf https://www.altera.com/en_US/pdfs/literature/an/an528.pdf [2] https://www.youtube.com/watch?v=A3qw_Ecx9Co https://www.youtube.com/watch?v=A3qw_Ecx9Co
Dylan16807 10y ago
Note that GDDR5 abandoned length matching, and just measures the latencies of each wire to calibrate itself.

3 ms·

DDR4-SDRAM achieves speeds in excess of 1.2 GHz over distances of 4" or more. That doesn't leave too much wiggle room.

by creshal 10y ago

DDR4-SDRAM achieves speeds in excess of 1.2 GHz over distances of 4" or more. That doesn't leave too much wiggle room.

iheartmemcache 10y ago
Surprisingly, the behavior at that speeds is fairly well known. I don't even think you need to move from FR4 to a more controlled material (e.g.generally in mmWave, Isola FR408, along with sometimes Rogers stuff, IME, is what is used). Allegro PCB SI(Signal Integrity) even models high speed timing fairly well at the design stage. You've got plenty of stuff at the test stage too. E.g., the gear on high-end Lecroy's metrology test gear is at 100ghz. Agilent (Keysight, whatever, it's still HP to me) has a full test rig for USB3.1[0] at 10gbps for their consumer level gear (again, fairly slow). Step it up to FPGA speeds and here's[1] an app-note by Altera with way higher speeds. Here's a really brief overview of 'rules of thumb' that work up to PCI-e[2] by TI. 50 minutes and worth a watch. Clean power that won't couple in, matching lines lengths on diff pairs, proper isolated ground planes (give AGND and DGND their own layers) and proper termination will easily get you 95% of the way there. (Shameless promotion-- available for high-speed design, pre-EMC compliance testing, fault diagnostics, etc). [0] http://www.keysight.com/en/pd-2472798-pn-U7243B/usb-31-compliance-test-software-for-infiniium-oscilloscopes?pm=PL&nid=-32976.1106319&cc=US&lc=eng http://www.keysight.com/en/pd-2472798-pn-U7243B/usb-31-compl... [1] https://www.altera.com/en_US/pdfs/literature/an/an528.pdf https://www.altera.com/en_US/pdfs/literature/an/an528.pdf [2] https://www.youtube.com/watch?v=A3qw_Ecx9Co https://www.youtube.com/watch?v=A3qw_Ecx9Co
Dylan16807 10y ago
Note that GDDR5 abandoned length matching, and just measures the latencies of each wire to calibrate itself.