5 ms·

Worrying about the speed of light in processor caching these days is like putting a spoiler on your cart and horse to reduce drag. It might matter eventually, a

Worrying about the speed of light in processor caching these days is like putting a spoiler on your cart and horse to reduce drag. It might matter eventually, and that's kind of cool to think about, but it's absurdly negligible with the technology of today. Processors today are orders of magnitude slower than that.

smallnamespace 10y ago
That's completely false. The speed of light today already constrains processor design (and by extension, on-CPU caches): http://arstechnica.com/science/2014/08/are-processors-pushing-up-against-the-limits-of-physics/ http://arstechnica.com/science/2014/08/are-processors-pushin... "Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other". Note that a light-nanosecond is about a foot, so I'm assuming this is talking about the propagation delay of electrons in silicon that need to go through gates, which I'm sure is much slower than light in a vacuum. To put this another way, you can view the scaling law as a hard upper bound on the speed of access to data; engineers can only approach that bound from below as technology improves. But given a certain level of technology, it's easier to make a faster L1 cache than an L2 cache, and that will hold even as we approach theoretical limits.
- creshal 10y ago
  > which I'm sure is much slower than light in a vacuum. Speed of signal in copper is about ⅔c, I suspect silicon will be in a similar ballbark – and the metal layers linking the silicon layers are made of copper anyway. So it's about 8"/ns… and the (three dimensional, 10+ layer) signal routes are anything but a straight line.
  - hamiltonkibbe 10y ago
    And the signals all need to get there at the same time
    - creshal 10y ago
      And that's such a hard problem that you don't even have to go down to CPU scale for it to matter. If you look at mainboards (or some smaller PCBs), the connecting lanes between e.g. RAM and CPU closer to the centre are often zigzagged, to match the lengths – and delays – of the necessarily longer outer lanes. The speed of light is actually really damn slow.
      - hamiltonkibbe 10y ago
        > The speed of light is actually really damn slow. I don't think one really appreciates that until they found out that after X hours of place&route they missed timing by some fraction of a nanosecond
      - Dylan16807 10y ago
        > you don't even have to go down to CPU scale for it to matter. It's say it's the opposite, really. The longer the wires, the more effort it takes to synchronize their delays within a certain number of picoseconds.
    - klodolph 10y ago
      Well, not entirely. For data signals in general you just need all the lines to resolve to the desired value before the clock. You do need to be very careful about the clock, though.
      - hamiltonkibbe 10y ago
        Well yeah, I figured that that's implied, the only times that really matter are the rising and falling edges of the clock.
      - creshal 10y ago
        DDR4-SDRAM achieves speeds in excess of 1.2 GHz over distances of 4" or more. That doesn't leave too much wiggle room.
        10y ago
  - klodolph 10y ago
    The speed of the signal depends on the properties of the surrounding medium though, right? You get one speed through copper in air but another speed entirely for copper in silicon.
    - creshal 10y ago
      And another for pure silicon, and others for the various doped silicons, … I don't even know what the actual materials are with current technologies, but whatever it is, the speed will be much lower than the vacuum speed of light.
      - emn13 10y ago
        Well, that depends on the context. You're totally right in general, but for the purpose of order-of-magnitudes of maximal clock rates, the speed of light hardly varies. I can't find any normal, plausible processor material with a refractive index of 4, let alone 10. So while light in silicon may well travel [almost 3.5 times](http://refractiveindex.info/?shelf=main&book=Si&page=Chandler-Horowitz http://refractiveindex.info/?shelf=main&book=Si&page=Chandle...) more slowly than in a vacuum - which is hardly nothing, at the granularity we're talking about I think it's not a huge issue. But that's just perspective - clearly the materials matter and will affect signal transmission speeds, and probably even today impose significant (if indirect) limitations. It's possible weird dopings or quantum effect change this dramatically, I suppose. But if I had to guess, they don't.
- klodolph 10y ago
  A bit of a nit: We're not worried about the propagation of electrons over distance as much as we're worried about the propagation of the electric field. Electrons move too slow, the electric field moves much faster. https://en.wikipedia.org/wiki/Velocity_factor https://en.wikipedia.org/wiki/Velocity_factor
- TheOtherHobbes 10y ago
  >"Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other". That's almost completely misleading. Except for the clock itself, nothing that happens inside a processor takes a single clock cycle. And clock distribution delays need compensation anyway. That's also true of memory. No one has ever seen 1-0-0-0 CAS RAM. (And no one ever will.) It's true that pushing up against distribution times makes topology more complicated and lowers the maximum possible speed. But that's actually the difference between electronics and photonics, which promise to run many orders of magnitude faster than EM-based silicon design. (I've seen "millions" quoted, but that may turn out to be hyperbole. Even so - optical fibre can run at tens of Tbps.) Of course there's a difference between transmission speed, which is a function of the speed of light, and maximum data rate, which is a function of bandwidth. But unlike electrons-in-silicon connections, photonics may not need to be 100% serial. It's entirely possible to get multiple data channels down a single line with frequency multiplexing, and perhaps also by phase rotation. That has huge potential to change the packing density and the speed of processor designs; potentially you could have processor elements that were massively parallel but connected with single lines. There's also some hope that because power dissipation shouldn't be such a problem, it will be easier to make 3D designs - although that's probably more speculative. Bottom line is silicon is nearly done, but photonics is just getting started. Like fusion power it's probably a couple of decades away, but when it arrives it will be huge.
  - emn13 10y ago
    So, what you're really saying is that it's quite accurate, there are just details and more details but in the end - as long as we use a single clock - signals need to be able to travel from one end to the other in a single clock cycle. Now, if we had (partially) clockless processors... Also, your details are a lot more misleading than those in the article. lots of things in a modern processor take 1 clock cycle. Agner has lovely tables:www.agner.org/optimize/ and note that most basic integer and floating point operations on a skylake processor take 1 cycle - things like bit shuffling, moving, adding (not floats), and quite a few incidental other operations. Now, I'm sure you can quibble that a latency of 1 cycle in that table isn't really 1 cycle under some unusual interpretation of what's going on, but at that point you're quibbling about what "doing something" means, which isn't helpful. What programmers/compiler writers call 1 clock cycle can execute what most people call 1 instruction for many common instructions, even today.
- Dylan16807 10y ago
  If anyone talks about signals crossing the chip in a single cycle, they're barking up the wrong tree. It's absolutely unnecessary. It would not take a tremendous engineering work to make a CPU where signals go no more than 3mm or even 1mm in a cycle. (At 5GHz you have a distance budget of over 40mm.) The most important constraint for single-threaded operation is transistor switching time. It's likely the most important constraint will always be transistor switching time.
  - pkolaczk 10y ago
    Transistor switching time is limited mostly by electrical capacity which is determined by the permittivity of the material the transistor is made from. And permittivity and permeablity are the only things determining the speed of light in a material. So saying that speed of light is the limiting factor of transistor switching time is valid.
aporetics 10y ago
Spoilers don't reduce drag. They produce downforce to counteract the lift effect of air moving under the car. It is only necessary at very high speeds, and prevents loss of grip in (especially) the rear tires. But, yeah, horse and buggy. I'm with you there.
- lasc4r 10y ago
  Spoilers reduce drag and provide down force and high speeds.
  - coredog64 10y ago
    Aerospace engineer here: Producing lift in either the up (airplane) or down (spoiler) direction generates induced drag. The amount depends on your design, in that a large real or effective AR can reduce it, but it's going to be there.
    - ScottBurson 10y ago
      I think what happens in automotive designs, which are not always penned with the same attention to aerodynamics as aerospace designs, is that they often have unintentional lift at the rear. Adding a small spoiler, then, doesn't add actual downforce, it just reduces lift -- and therefore reduces drag into the bargain.
- tankenmate 10y ago
  The downforce isn't there to counteract air under the car (actually fast flowing air under the car produces downforce; read up on ground effect and Bernoulli). The downforce is there so the car can go around corners quicker; the downforce increases the friction (Ff<=mu x Fn), i.e. the force of friction is less than or equal to the coefficient of friction (mu / μ) multiplied by the normal force. In the case of a tire the normal force is the downward force (provided by the wings or spoilers). Therefore the more downward force the higher the friction hence the more the tire can exert lateral force (cornering force). For example a F1 car at high speed can exert approximately 4Gs of lateral force when cornering, or 5Gs of force when breaking (at slower speeds a F1 car can't brake as hard).

smallnamespace 10y ago

That's completely false. The speed of light today already constrains processor design (and by extension, on-CPU caches): http://arstechnica.com/science/2014/08/are-processors-pushing-up-against-the-limits-of-physics/ http://arstechnica.com/science/2014/08/are-processors-pushin... "Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other". Note that a light-nanosecond is about a foot, so I'm assuming this is talking about the propagation delay of electrons in silicon that need to go through gates, which I'm sure is much slower than light in a vacuum. To put this another way, you can view the scaling law as a hard upper bound on the speed of access to data; engineers can only approach that bound from below as technology improves. But given a certain level of technology, it's easier to make a faster L1 cache than an L2 cache, and that will hold even as we approach theoretical limits.

creshal 10y ago
> which I'm sure is much slower than light in a vacuum. Speed of signal in copper is about ⅔c, I suspect silicon will be in a similar ballbark – and the metal layers linking the silicon layers are made of copper anyway. So it's about 8"/ns… and the (three dimensional, 10+ layer) signal routes are anything but a straight line.
- hamiltonkibbe 10y ago
  And the signals all need to get there at the same time
  - creshal 10y ago
    And that's such a hard problem that you don't even have to go down to CPU scale for it to matter. If you look at mainboards (or some smaller PCBs), the connecting lanes between e.g. RAM and CPU closer to the centre are often zigzagged, to match the lengths – and delays – of the necessarily longer outer lanes. The speed of light is actually really damn slow.
    - hamiltonkibbe 10y ago
      > The speed of light is actually really damn slow. I don't think one really appreciates that until they found out that after X hours of place&route they missed timing by some fraction of a nanosecond
    - Dylan16807 10y ago
      > you don't even have to go down to CPU scale for it to matter. It's say it's the opposite, really. The longer the wires, the more effort it takes to synchronize their delays within a certain number of picoseconds.
  - klodolph 10y ago
    Well, not entirely. For data signals in general you just need all the lines to resolve to the desired value before the clock. You do need to be very careful about the clock, though.
    - hamiltonkibbe 10y ago
      Well yeah, I figured that that's implied, the only times that really matter are the rising and falling edges of the clock.
    - creshal 10y ago
      DDR4-SDRAM achieves speeds in excess of 1.2 GHz over distances of 4" or more. That doesn't leave too much wiggle room.
      - 10y ago
- klodolph 10y ago
  The speed of the signal depends on the properties of the surrounding medium though, right? You get one speed through copper in air but another speed entirely for copper in silicon.
  - creshal 10y ago
    And another for pure silicon, and others for the various doped silicons, … I don't even know what the actual materials are with current technologies, but whatever it is, the speed will be much lower than the vacuum speed of light.
    - emn13 10y ago
      Well, that depends on the context. You're totally right in general, but for the purpose of order-of-magnitudes of maximal clock rates, the speed of light hardly varies. I can't find any normal, plausible processor material with a refractive index of 4, let alone 10. So while light in silicon may well travel [almost 3.5 times](http://refractiveindex.info/?shelf=main&book=Si&page=Chandler-Horowitz http://refractiveindex.info/?shelf=main&book=Si&page=Chandle...) more slowly than in a vacuum - which is hardly nothing, at the granularity we're talking about I think it's not a huge issue. But that's just perspective - clearly the materials matter and will affect signal transmission speeds, and probably even today impose significant (if indirect) limitations. It's possible weird dopings or quantum effect change this dramatically, I suppose. But if I had to guess, they don't.
klodolph 10y ago
A bit of a nit: We're not worried about the propagation of electrons over distance as much as we're worried about the propagation of the electric field. Electrons move too slow, the electric field moves much faster. https://en.wikipedia.org/wiki/Velocity_factor https://en.wikipedia.org/wiki/Velocity_factor
TheOtherHobbes 10y ago
>"Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other". That's almost completely misleading. Except for the clock itself, nothing that happens inside a processor takes a single clock cycle. And clock distribution delays need compensation anyway. That's also true of memory. No one has ever seen 1-0-0-0 CAS RAM. (And no one ever will.) It's true that pushing up against distribution times makes topology more complicated and lowers the maximum possible speed. But that's actually the difference between electronics and photonics, which promise to run many orders of magnitude faster than EM-based silicon design. (I've seen "millions" quoted, but that may turn out to be hyperbole. Even so - optical fibre can run at tens of Tbps.) Of course there's a difference between transmission speed, which is a function of the speed of light, and maximum data rate, which is a function of bandwidth. But unlike electrons-in-silicon connections, photonics may not need to be 100% serial. It's entirely possible to get multiple data channels down a single line with frequency multiplexing, and perhaps also by phase rotation. That has huge potential to change the packing density and the speed of processor designs; potentially you could have processor elements that were massively parallel but connected with single lines. There's also some hope that because power dissipation shouldn't be such a problem, it will be easier to make 3D designs - although that's probably more speculative. Bottom line is silicon is nearly done, but photonics is just getting started. Like fusion power it's probably a couple of decades away, but when it arrives it will be huge.
- emn13 10y ago
  So, what you're really saying is that it's quite accurate, there are just details and more details but in the end - as long as we use a single clock - signals need to be able to travel from one end to the other in a single clock cycle. Now, if we had (partially) clockless processors... Also, your details are a lot more misleading than those in the article. lots of things in a modern processor take 1 clock cycle. Agner has lovely tables:www.agner.org/optimize/ and note that most basic integer and floating point operations on a skylake processor take 1 cycle - things like bit shuffling, moving, adding (not floats), and quite a few incidental other operations. Now, I'm sure you can quibble that a latency of 1 cycle in that table isn't really 1 cycle under some unusual interpretation of what's going on, but at that point you're quibbling about what "doing something" means, which isn't helpful. What programmers/compiler writers call 1 clock cycle can execute what most people call 1 instruction for many common instructions, even today.
Dylan16807 10y ago
If anyone talks about signals crossing the chip in a single cycle, they're barking up the wrong tree. It's absolutely unnecessary. It would not take a tremendous engineering work to make a CPU where signals go no more than 3mm or even 1mm in a cycle. (At 5GHz you have a distance budget of over 40mm.) The most important constraint for single-threaded operation is transistor switching time. It's likely the most important constraint will always be transistor switching time.
- pkolaczk 10y ago
  Transistor switching time is limited mostly by electrical capacity which is determined by the permittivity of the material the transistor is made from. And permittivity and permeablity are the only things determining the speed of light in a material. So saying that speed of light is the limiting factor of transistor switching time is valid.

aporetics 10y ago

Spoilers don't reduce drag. They produce downforce to counteract the lift effect of air moving under the car. It is only necessary at very high speeds, and prevents loss of grip in (especially) the rear tires. But, yeah, horse and buggy. I'm with you there.

lasc4r 10y ago
Spoilers reduce drag and provide down force and high speeds.
- coredog64 10y ago
  Aerospace engineer here: Producing lift in either the up (airplane) or down (spoiler) direction generates induced drag. The amount depends on your design, in that a large real or effective AR can reduce it, but it's going to be there.
  - ScottBurson 10y ago
    I think what happens in automotive designs, which are not always penned with the same attention to aerodynamics as aerospace designs, is that they often have unintentional lift at the rear. Adding a small spoiler, then, doesn't add actual downforce, it just reduces lift -- and therefore reduces drag into the bargain.
tankenmate 10y ago
The downforce isn't there to counteract air under the car (actually fast flowing air under the car produces downforce; read up on ground effect and Bernoulli). The downforce is there so the car can go around corners quicker; the downforce increases the friction (Ff<=mu x Fn), i.e. the force of friction is less than or equal to the coefficient of friction (mu / μ) multiplied by the normal force. In the case of a tire the normal force is the downward force (provided by the wings or spoilers). Therefore the more downward force the higher the friction hence the more the tire can exert lateral force (cornering force). For example a F1 car at high speed can exert approximately 4Gs of lateral force when cornering, or 5Gs of force when breaking (at slower speeds a F1 car can't brake as hard).