4 ms·

I don't see why branching is so hard -- it's two cycles to test the branch, one more if the branch is taken, one more if it crosses a page boundary! /6502joke

by sehugg 10y ago

pawadu 10y ago
well... for the size of its pipeline (1?) and the amount of speculative execution going on (0) the non-existing branch prediction of 6502 was basically optimal.
- Someone 10y ago
  The 6502 has a tiny bit of pipeline/speculative execution. The CPU fetches the next instruction before the current one has finished. http://www.atarihq.com/danb/files/64doc.txt http://www.atarihq.com/danb/files/64doc.txt: "If an instruction does not store data in memory on its last cycle, the processor can fetch the opcode of the next instruction while executing the last cycle." The 6502 also sometimes does excess reads and writes. For example, "Read-modify-write instructions (like INC) read the original data, write it back, and then write the modified data." (http://forum.6502.org/viewtopic.php?t=2 http://forum.6502.org/viewtopic.php?t=2). One could call that speculative execution, where the processor writes back the value, just in case adding one to it doesn't increase it, and then, having discovered that adding one changes the value, writes the right value :-)
  - phire 10y ago
    The 6502 had no concept of not doing a memory operation. Either it's doing a read or it's doing a write, there is no option to use the bus unused. So the 6502 spams dummy reads and occasionally dummy writes whenever it's doing something internally. Edit: And that's not the only interesting thing I've learned recently about the 6502, There is a very good reason why the stack is on page 1 and not some other constant page. There are only 3 constant values which can be pushed on the SB/ADH buses, 0xff, 0x00 and 0x01. Ox00 is loaded into upper address register for zero page instructions. For Push operations, it loads 0x01 into the upper address register and puts the stack pointer + 0xff into the adder, which subtracts one from the stack pointer. (The 0xff is just the default bus value, if nothing else is pulling it low, so you get it for free) For Pop operations, it pushes the same 0x01 into both the upper address register and the adder, at the same time. So if they wanted to put the stack page at another constant page, or at a variable page they would also need to provide more gates to provide another constant one somewhere.

I don't see why branching is so hard -- it's two cycles to test the branch, one more if the branch is taken, one more if it crosses a page boundary! /6502joke

by sehugg 10y ago

I don't see why branching is so hard -- it's two cycles to test the branch, one more if the branch is taken, one more if it crosses a page boundary! /6502joke

pawadu 10y ago

well... for the size of its pipeline (1?) and the amount of speculative execution going on (0) the non-existing branch prediction of 6502 was basically optimal.

Someone 10y ago
The 6502 has a tiny bit of pipeline/speculative execution. The CPU fetches the next instruction before the current one has finished. http://www.atarihq.com/danb/files/64doc.txt http://www.atarihq.com/danb/files/64doc.txt: "If an instruction does not store data in memory on its last cycle, the processor can fetch the opcode of the next instruction while executing the last cycle." The 6502 also sometimes does excess reads and writes. For example, "Read-modify-write instructions (like INC) read the original data, write it back, and then write the modified data." (http://forum.6502.org/viewtopic.php?t=2 http://forum.6502.org/viewtopic.php?t=2). One could call that speculative execution, where the processor writes back the value, just in case adding one to it doesn't increase it, and then, having discovered that adding one changes the value, writes the right value :-)
- phire 10y ago
  The 6502 had no concept of not doing a memory operation. Either it's doing a read or it's doing a write, there is no option to use the bus unused. So the 6502 spams dummy reads and occasionally dummy writes whenever it's doing something internally. Edit: And that's not the only interesting thing I've learned recently about the 6502, There is a very good reason why the stack is on page 1 and not some other constant page. There are only 3 constant values which can be pushed on the SB/ADH buses, 0xff, 0x00 and 0x01. Ox00 is loaded into upper address register for zero page instructions. For Push operations, it loads 0x01 into the upper address register and puts the stack pointer + 0xff into the adder, which subtracts one from the stack pointer. (The 0xff is just the default bus value, if nothing else is pulling it low, so you get it for free) For Pop operations, it pushes the same 0x01 into both the upper address register and the adder, at the same time. So if they wanted to put the stack page at another constant page, or at a variable page they would also need to provide more gates to provide another constant one somewhere.