12 ms·
Ouch! Appeal to authority stings. But in response, I pitted mighty Google against Intel and in the first ten hits for "cache coherence scalability paper" I foun
by _yosefk 10y ago
Ouch! Appeal to authority stings. But in response, I pitted mighty Google against Intel and in the first ten hits for "cache coherence scalability paper" I found the one that prompted me to write my original comment:
From http://people.ee.duke.edu/~sorin/papers/tr2011-1-coherence.pdf http://people.ee.duke.edu/~sorin/papers/tr2011-1-coherence.p...
"Using amortized analysis, we show that interconnection network traffic per miss need not grow with core count and that coherence uses at most 20% more traffic per miss than a system with caches but not coherence. Using hierarchical design, we show that storage overhead can be made to grow as the root of core count and stay small, e.g., 2% of total cache size for even 512 cores.
Consequently, we predict that on-chip coherence is here to stay. Computer systems tend not abandon compatibility to eliminate small costs, such as the costs we find for scaling coherence"
And now the quote from TFA:
"Do we really need cache coherency across a hundred cores or a thousand cores on a die?"
The paper's 512 cores are in the middle of the range where TFA suggests you start to get enough problems to seriously consider breaking compatibility and foregoing cache coherence. Why is the paper which supports its claims with concrete analysis less credible than an unsupported offhand remark from someone at Intel, a company that made a fortune from all of its CPU designs except that infamous one where they abandoned compatibility?
BTW a basic understanding of coherence might lead one to doubt the claims about lack of scalability. When you hit the cache, you know that you own the data so it's fast. When you miss the cache, it's a very slow operation anyway, the overhead of checking whether to fetch the data from external memory or another cache can't be that bad. And if data travels a lot from one cache to another because of true or false sharing, that's the fault of the code doing that. Coherence is not supposed to make sharing blindingly fast, just to make it correct, and to make false sharing correct as well.
Of course none of this will be relevant if there's no substrate on which to put a thousand of x86 cores, which right now there isn't.
- imtringued 10y agoIf that's true why didn't they incorporate this into their products? They had 5 years. That's plenty of time in this industry.
- _yosefk 10y agoAll multi-core Intel chips have cache coherence. Intel might not have incorporated the paper's approach to scaleable cache coherence because they don't have a substrate to put 512 x86 cores on.
- jcranmer 10y ago> BTW a basic understanding of coherence might lead one to doubt the claims about lack of scalability. When you hit the cache, you know that you own the data so it's fast. When you miss the cache, it's a very slow operation anyway, the overhead of checking whether to fetch the data from external memory or another cache can't be that bad. And if data travels a lot from one cache to another because of true or false sharing, that's the fault of the code doing that. Coherence is not supposed to make sharing blindingly fast, just to make it correct, and to make false sharing correct as well. The problem isn't so much that missing the cache is slow, but rather how do you make a processor know that it has to look the data value up in another cache instead of main memory? The two main options are either to basically broadcast every request to every cache it might be in, or to store in main memory which cache it's in--you have a design tradeoff between high interconnect traffic or high memory metadata usage.
- _yosefk 10y agoYou don't store it in main memory, you store it in the directory, aka snoop filter, or whatever you want to call it. The paper actually estimated the overhead and came up with the number 2% for 512 cores, not that high.
- jcranmer 10y agoThe directory is basically main memory, as far as provisioning bits of storage are concerned. The number 2% also is achieved only if you do three-tier organization of processors, and (IIRC) you need to limit the cache broadcasts to within each tier--which puts some sharp constraints on how you lay out cores in a chip. Intel's many-core chips, IIRC, are laid out in a single ring connecting all the cores, which means it's completely the wrong topology implied by the paper.