7 ms·

To be perfectly clear: the 1000x claim isn't about throughput, but latency. The graph in the article makes this clear: spinning drives have latencies on the ord

To be perfectly clear: the 1000x claim isn't about throughput, but latency. The graph in the article makes this clear: spinning drives have latencies on the order of 10ms, NAND flash about 10us, and DRAM about 1ns. The claim is that Optane will achieve latencies on the order of 10ns, or 1000x better than NAND. The on-stage benchmark shows a write throughput of about 2GB/s, which is a much more modest improvement over the 500MB/s of a modern consumer SSD (and perfectly within reason for a PCI x2 interface).

Koromix 10y ago
Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Assuming we keep the file system model, I'm guessing some kind of direct memory mapping is in order? Anyone knows what's ahead of us on the software side, to take advantage of this kind of latency?
- rubber_duck 10y ago
  What's wrong with plain old mmap ?
  - Koromix 10y ago
    mmap() tricks you into thinking you can directly access the disk. What really happens when you access the mapped data is that the CPU generates a page fault, the OS takes control, copies the data from disk to physical memory and maps the page in your address space. So essentially it is a convient way to do read(). The mmap() model is good. The current page fault mechanism, not so much.
    - rayiner 10y ago
      The difference is that you only take the page fault once per page (or less than once if you do some prefetching in the kernel), while you have to do a system call for every read().
  - _wmd 10y ago
    It costs a fortune to map a file on every OS I've tried, it makes little sense unless you're consuming a lot of data from few files rather than little data from many files
- wmf 10y ago
  http://pmem.io/ http://pmem.io/
- cleech 10y ago
  Memory addressable non-volatile storage instead of SSDs that process block storage read/write commands, and file-system improvements to allow direct mmap of file contents from NVM into your process address space without copying through RAM.
- jacquesm 10y ago
  Files exist because persistent storage is slow, copying data from RAM to disk is slow and we'd like to have a way to refer by name to blobs of bytes, but in the end it is only there because it's a useful metaphor. If the metaphor gets in the way of our ability to use the storage medium you can either do a mapping (like the direct memory mapping you refer to), which in this case would almost be like a backwards compatibility layer, a more involved scheme where all RAM is backed by persistent storage and devices only keep a flag which objects are currently being worked on and which are stable (an 'open' file would simply be marked as currently in use by an application but there would be no explicit save, just an unlock), or a completely new system based on an image like architecture (see: smalltalk, some lisp implementations). There are some drawbacks to that model (such as harder collaborative development) but I see no reason that applications could not be packaged that way even if the development used a more traditional method. It would be fairly trivial to layer a conventional filesystem on top of such a persistent object store to get the best of both worlds, which would - amongst others - give you instantaneous suspend and re-awaken and other goodies. If true this will vastly change the way we use computers.
  - gumby 10y ago
    This was the original architecture of Multics BTW -- the world just consisted of a single address space of segments (pages) plus a capability-based address space; a higher level construct gave you a named structure for a group of segments. A similar approach has been taken with HP's interesting memristor-based "Machine" There's a lot of interesting stuff in Organick's book on Multics, not all of which was implemented, unfortunately. And a lot of really good stuff was tossed overboard when fitting Unix into a PDP-7 (a lot of overwrought bad stuff was jettisoned too -- don't get the wrong idea!).
- gjulianm 10y ago
  I'm curious, why do you say that the open/read/write model can't work? I suppose that current software should be optimized to take advantage of better performance, but I don't see why it is obsolete.
  - nneonneo 10y ago
    10ns latency means that a file entry/inode/block is available just 10-30 CPU cycles after it is requested. Suddenly the 1000 CPU cycles spent dispatching the system call look very inefficient by comparison. Obsolete might not be the right term, but there is essentially no way that open/read/write can take proper advantage of this kind of low latency storage. We are going to need a new way to abstract and interface with this persistent storage.
    - gpderetta 10y ago
      Or a way to make system calls faster, some sort of vdso with the ability to switch privilege level.
      - jdub 10y ago
        That's how __vsyscall works now.
        gpderetta 10y ago
        __vsyscall simply abstracts away the actual system call invocation strategy (int, sysenter, syscall), but doesn't change the model at all. Anyway, what I was thinking was similar to call gates, which were phased out for being slow. Probably just making syscall faster in the CPU and reducing the overhead kernel side would be enough.
    - bdonlan 10y ago
      Read/write are certainly a bit slow, but this may well be acceptable for most applications. High performance apps can use mmap, which can be extended to directly map the nonvolatile memory in question.
- benlwalker 10y ago
  http://pmem.io http://pmem.io - for byte addressable form factors http://spdk.io http://spdk.io - for block device form factors
- coldtea 10y ago
  >Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Citation needed.
- nneonneo 10y ago
  This is a great question. One way I imagine it: Short term, the disk controller becomes a peripheral on the memory bus. On a 64-bit x86-64 system, the top 16 bits of the address are either 0000 or ffff for RAM. Make it so that the prefix 1000 (for example) maps to the disk, so accessing (physical) address 1000000013371000 accesses byte 13371000 on the disk. Now processes can just ask the OS to perform a physical memory mapping to obtain a range of virtual addresses directly backed by disk pages, with page protections set based on their filesystem permissions. Such physical address mapping interfaces already exists in most OSes to support memory mapped I/O (for example, mapping /dev/mem in Linux). This addressing scheme has another advantage: other devices on the system can use e.g. DMA to directly talk to the disk without any CPU intervention. For example, the GPU could load textures straight off of disk, just like John Carmack wants. Medium term, we start rethinking the filesystem. If we make the address range for a given disk completely persistent, we can just put pointers to disk bytes on the disk itself. Processes will use the same virtual addresses as the physical addresses when talking to the disk. Suddenly "serialization" to disk is no longer required: data structures can be stored in native form directly on the disk. Imagine having a "dmalloc" function call hand you a chunk of persistent storage which you treat the same as any memory, but which can outlive the process. Similar concepts exist in some languages (like MUMPS), and now we bring the idea to all programming environments. Long term, RAM ceases to be an independent entity, and merely becomes OS-managed cache for the big persistent storage (assuming it still has any latency/bandwidth advantages by this point). Now you can get rid of the notion of "shutting down" or "starting up" the system: everything is persistent. Without having to constantly refresh DRAM to keep the system alive, devices can "sleep/hibernate" more frequently and readily, saving significant power. Programming models become nearly unrecognizable as old models of memory management and process lifetimes give way to new models of persistent storage management and eternal services. We're not far off from seeing a potential revolution in computing here.
  - imtringued 10y ago
    >Suddenly "serialization" to disk is no longer required That's not true. You'd still want excel to just save your sheets as xls file and show it to a coworker as opposed to sharing the entire excel program state. Upgrading from one version to another also requires a stable persistent data format for things such as configurations. Not to mention that you still need serialization to communicate over a network.
- imtringued 10y ago
  For now. If you build it they will come. Things like these take time but they won't happen if the hardware guys don't move first.
- Qantourisc 10y ago
  The main reason to keep it are: 1) network 2) what if we uncover a faster cpu/mem ? We would need to reintroduce file-systems. I'd say it's safe to deprecate it after about 30 years after it become obsolete. (So we are sure nothing will surpass it any time soon.)
jacquesm 10y ago
It's a game changer either way, and it will be one more nail in the coffin of anything mechanical.
- zer00eyz 10y ago
  For consumer, and "online" hardware I fully agree, but were going to have tape for a long time to come. As a medium, for offline, offsite it still reigns king. Density, reliably, and durability remain high, vs platter based drives or SSD. I know of at least two companies that keep tape going for compliance reasons. At the end of each year, they do a pretty large archival snapshot, and send it off to storage. It will remain there till some lawyer asks for it, and will most likely end up copied by a third party for the sake of integrity. For one of them, the archive tapes are becoming a concern, the media is fine, but finding hardware is going to become a problem.
  - deleted 10y ago
    [deleted]
  - a_imho 10y ago
    There are some interesting regulations in finance, I know at least one bank that keeps offline backups on tapes, but wonder how often do they test it. My experience with them tells me, they are not the most tech savvy bunch. If they ever need to use backups with the software they were provided decades ago / by modern fast failing agile company (according to taste), even if they can get the source it will be very hard to compile and run them. Reproducible builds is not exactly a solved problem.
    - y4mi 10y ago
      they need to put their entire environment into docker container and archive the images! theyll be able to recreate their whole environment at any time in the future! ...ill see myself out
    - ashitlerferad 10y ago
      > Reproducible builds is not exactly a solved problem. Indeed, but we are getting there (over 90% of packages from Debian stretch amd64 and 99.9% of OpenWRT packages): https://tests.reproducible-builds.org/debian/ https://tests.reproducible-builds.org/debian/ https://tests.reproducible-builds.org/openwrt/ https://tests.reproducible-builds.org/openwrt/
eloff 10y ago
DRAM does not have 1ns latency! On a 4ghz skylake chip you can access the L1 cache at 1ns. DRAM is going to be more in the range of 60(local)-100(remote) nanoseconds. Optane will likely be > 300ns latency from what I've heard, if you access it directly through the CPU memory controller via loads and stores, which is still very impressive.
- nneonneo 10y ago
  I'm quoting from the graph in the article. The numbers are also meant to be "on the order of", since the graph only provides that level of detail - so, for example, 1ns really means "1-9ns". I believe that they are using fairly best-case latency numbers, under the assumption that the memory accesses are close to sequential. For random memory accesses, as you note, the latencies are higher. Unfortunately the article doesn't go into detail on what Optane's worst-case latencies are, nor what the latencies will be like in a real functional system (mostly because Intel has only early prototypes to show).
  - eloff 10y ago
    Yeah, I wouldn't do that, that graph is hardly accurate. 9ns won't get you a L3 cache hit on most skylake chips, nevermind main memory. For sequential access giving a latency number doesn't make sense - you need to talk throughput. You can get upwards of 20gb/s with a single core for DRAM. Here you're at least bounded by the 4x PCI interface (more likely the Optane device) so maybe 3GB/s if you're feeling generous.
- chongli 10y ago
  When we talk about 1ns latency for DRAM we aren't talking about access latency, we're talking about CAS latency[0]. This is how fast the DRAM actually works. It doesn't include the rest of the overhead between the time the data is sent over the bus and the time it's loaded into a register and ready for an instruction to operate on it. CAS latency for DDR3-3300 is less than 1/3ns, according to the article below. If Intel's new Optane memory can achieve addressing on the order of 10ns, it will be very competitive with DRAM, since all of other overhead along the data path ought to be similar. [0] https://en.wikipedia.org/wiki/CAS_latency https://en.wikipedia.org/wiki/CAS_latency
ChuckMcM 10y ago
Ok, a couple of things. First, I found it really amazing at how convoluted Intel plotted their numbers on that latency graph so that it would "Up and to the right" which everyone "knows" is good. The second thing is that Intel has been claiming multiple GB/second of throughput as well. They really do believe this will be a replacement for DRAM on some platforms. As in you read into your L3 case from this stuff and you flush to it when you write out a dirty cache lines. And while that will make the overall system slower, it gives it literally instant stop/start capability if the key parts of your architecture are static (can retain data at 0 clock). What that means is a laptop that can turn it self off between waiting for sectors to read in from the disk or packets to come off the network, or keys to be pressed by the user. Non-illuminated run times in days off of a battery source rather than hours. Imagine a 1.2TB of this stuff on the motherboard substituting for DRAM. So you've got every application and all the data for your applications already "in memory" as far as the chip is concerned. App switching? Instant, app data availability? instant. Quite a different experience than what we have today.
- visarga 10y ago
  > Quite a different experience than what we have today. For example, I only have to wait at most one second for an app to load, if it's not already open and minimized. It's comparable to the time it takes me to click a button. And my computer is rebooted only once every few months, so it's always up. This improvement will be more meaningful for random access database operations.
- simula67 10y ago
  Is this technology costly ? EDIT: Does not seem to be. “You could put the cost somewhere between NAND and DRAM. Cost per bit, it’s likely to be in between them somewhere. But actual cost will result from the products we bring to the marketplace.” http://hothardware.com/news/intel-and-micron-jointly-drop-disruptive-game-changing-3d-xpoint-cross-point-memory-1000x-faster-than-nand http://hothardware.com/news/intel-and-micron-jointly-drop-di...
- sspiff 10y ago
  > What that means is a laptop that can turn it self off between waiting for sectors to read in from the disk or packets to come off the network, or keys to be pressed by the user. Yeah, no. It might be able to turn of the CPU, but everything else would have to keep running. Graphics hardware does not deal well with frequent state changes. Network hardware would still need to run to keep its clock in sync with the signal. So, you get to turn off a handful of components, which is where we already are today - CPUs spend most of their time in deep sleep states. USB devices and chipsets implement sleep states. Graphics hardware clocks down significantly.
todd8 10y ago
To put these latency numbers in perspective 1ns is about 11 inches at the speed of light.
- umanwizard 10y ago
  Or three cycles on a typical desktop CPU.
  - todd8 10y ago
    Yes, but even one round trip to the store could blow most of your latency budget. The store will have to be right next to the processor.
Unklejoe 10y ago
I wonder what the actual latency improvements will be. If it's connected through PCI express, there will be a lower limit which is dictated by the bus. While reducing the latency of the drive will still certainly matter, this latency introduced by the bus will serve to lessen the relative improvements with respect to SSDs. PCI Express is packetized and it takes a little over 1 nanosecond per byte for the 3.0 version. I believe the minimum packet size is 20 bytes, but I'm not positive on that. It seems like the latency could never be less than 2 * (1 * 20) nanoseconds in the case of a random access, and this is before the latency of the drive itself is factored in. Surely there will be a few clock cycles required for the drive HW to decode the PCIe transaction and act upon it. That being said, any latency improvement of the drive _will_ have a direct reduction in effective latency in the end, so it’s all good news to me. I’m just curious about the 1000x figure that’s being referenced everywhere.

Koromix 10y ago

Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Assuming we keep the file system model, I'm guessing some kind of direct memory mapping is in order? Anyone knows what's ahead of us on the software side, to take advantage of this kind of latency?

rubber_duck 10y ago
What's wrong with plain old mmap ?
- Koromix 10y ago
  mmap() tricks you into thinking you can directly access the disk. What really happens when you access the mapped data is that the CPU generates a page fault, the OS takes control, copies the data from disk to physical memory and maps the page in your address space. So essentially it is a convient way to do read(). The mmap() model is good. The current page fault mechanism, not so much.
  - rayiner 10y ago
    The difference is that you only take the page fault once per page (or less than once if you do some prefetching in the kernel), while you have to do a system call for every read().
- _wmd 10y ago
  It costs a fortune to map a file on every OS I've tried, it makes little sense unless you're consuming a lot of data from few files rather than little data from many files
wmf 10y ago
http://pmem.io/ http://pmem.io/
cleech 10y ago
Memory addressable non-volatile storage instead of SSDs that process block storage read/write commands, and file-system improvements to allow direct mmap of file contents from NVM into your process address space without copying through RAM.
jacquesm 10y ago
Files exist because persistent storage is slow, copying data from RAM to disk is slow and we'd like to have a way to refer by name to blobs of bytes, but in the end it is only there because it's a useful metaphor. If the metaphor gets in the way of our ability to use the storage medium you can either do a mapping (like the direct memory mapping you refer to), which in this case would almost be like a backwards compatibility layer, a more involved scheme where all RAM is backed by persistent storage and devices only keep a flag which objects are currently being worked on and which are stable (an 'open' file would simply be marked as currently in use by an application but there would be no explicit save, just an unlock), or a completely new system based on an image like architecture (see: smalltalk, some lisp implementations). There are some drawbacks to that model (such as harder collaborative development) but I see no reason that applications could not be packaged that way even if the development used a more traditional method. It would be fairly trivial to layer a conventional filesystem on top of such a persistent object store to get the best of both worlds, which would - amongst others - give you instantaneous suspend and re-awaken and other goodies. If true this will vastly change the way we use computers.
- gumby 10y ago
  This was the original architecture of Multics BTW -- the world just consisted of a single address space of segments (pages) plus a capability-based address space; a higher level construct gave you a named structure for a group of segments. A similar approach has been taken with HP's interesting memristor-based "Machine" There's a lot of interesting stuff in Organick's book on Multics, not all of which was implemented, unfortunately. And a lot of really good stuff was tossed overboard when fitting Unix into a PDP-7 (a lot of overwrought bad stuff was jettisoned too -- don't get the wrong idea!).
gjulianm 10y ago
I'm curious, why do you say that the open/read/write model can't work? I suppose that current software should be optimized to take advantage of better performance, but I don't see why it is obsolete.
- nneonneo 10y ago
  10ns latency means that a file entry/inode/block is available just 10-30 CPU cycles after it is requested. Suddenly the 1000 CPU cycles spent dispatching the system call look very inefficient by comparison. Obsolete might not be the right term, but there is essentially no way that open/read/write can take proper advantage of this kind of low latency storage. We are going to need a new way to abstract and interface with this persistent storage.
  - gpderetta 10y ago
    Or a way to make system calls faster, some sort of vdso with the ability to switch privilege level.
    - jdub 10y ago
      That's how __vsyscall works now.
      - gpderetta 10y ago
        __vsyscall simply abstracts away the actual system call invocation strategy (int, sysenter, syscall), but doesn't change the model at all. Anyway, what I was thinking was similar to call gates, which were phased out for being slow. Probably just making syscall faster in the CPU and reducing the overhead kernel side would be enough.
  - bdonlan 10y ago
    Read/write are certainly a bit slow, but this may well be acceptable for most applications. High performance apps can use mmap, which can be extended to directly map the nonvolatile memory in question.
benlwalker 10y ago
http://pmem.io http://pmem.io - for byte addressable form factors http://spdk.io http://spdk.io - for block device form factors
coldtea 10y ago
>Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Citation needed.
nneonneo 10y ago
This is a great question. One way I imagine it: Short term, the disk controller becomes a peripheral on the memory bus. On a 64-bit x86-64 system, the top 16 bits of the address are either 0000 or ffff for RAM. Make it so that the prefix 1000 (for example) maps to the disk, so accessing (physical) address 1000000013371000 accesses byte 13371000 on the disk. Now processes can just ask the OS to perform a physical memory mapping to obtain a range of virtual addresses directly backed by disk pages, with page protections set based on their filesystem permissions. Such physical address mapping interfaces already exists in most OSes to support memory mapped I/O (for example, mapping /dev/mem in Linux). This addressing scheme has another advantage: other devices on the system can use e.g. DMA to directly talk to the disk without any CPU intervention. For example, the GPU could load textures straight off of disk, just like John Carmack wants. Medium term, we start rethinking the filesystem. If we make the address range for a given disk completely persistent, we can just put pointers to disk bytes on the disk itself. Processes will use the same virtual addresses as the physical addresses when talking to the disk. Suddenly "serialization" to disk is no longer required: data structures can be stored in native form directly on the disk. Imagine having a "dmalloc" function call hand you a chunk of persistent storage which you treat the same as any memory, but which can outlive the process. Similar concepts exist in some languages (like MUMPS), and now we bring the idea to all programming environments. Long term, RAM ceases to be an independent entity, and merely becomes OS-managed cache for the big persistent storage (assuming it still has any latency/bandwidth advantages by this point). Now you can get rid of the notion of "shutting down" or "starting up" the system: everything is persistent. Without having to constantly refresh DRAM to keep the system alive, devices can "sleep/hibernate" more frequently and readily, saving significant power. Programming models become nearly unrecognizable as old models of memory management and process lifetimes give way to new models of persistent storage management and eternal services. We're not far off from seeing a potential revolution in computing here.
- imtringued 10y ago
  >Suddenly "serialization" to disk is no longer required That's not true. You'd still want excel to just save your sheets as xls file and show it to a coworker as opposed to sharing the entire excel program state. Upgrading from one version to another also requires a stable persistent data format for things such as configurations. Not to mention that you still need serialization to communicate over a network.
imtringued 10y ago
For now. If you build it they will come. Things like these take time but they won't happen if the hardware guys don't move first.
Qantourisc 10y ago
The main reason to keep it are: 1) network 2) what if we uncover a faster cpu/mem ? We would need to reintroduce file-systems. I'd say it's safe to deprecate it after about 30 years after it become obsolete. (So we are sure nothing will surpass it any time soon.)

jacquesm 10y ago

It's a game changer either way, and it will be one more nail in the coffin of anything mechanical.

zer00eyz 10y ago
For consumer, and "online" hardware I fully agree, but were going to have tape for a long time to come. As a medium, for offline, offsite it still reigns king. Density, reliably, and durability remain high, vs platter based drives or SSD. I know of at least two companies that keep tape going for compliance reasons. At the end of each year, they do a pretty large archival snapshot, and send it off to storage. It will remain there till some lawyer asks for it, and will most likely end up copied by a third party for the sake of integrity. For one of them, the archive tapes are becoming a concern, the media is fine, but finding hardware is going to become a problem.
- deleted 10y ago
  [deleted]
- a_imho 10y ago
  There are some interesting regulations in finance, I know at least one bank that keeps offline backups on tapes, but wonder how often do they test it. My experience with them tells me, they are not the most tech savvy bunch. If they ever need to use backups with the software they were provided decades ago / by modern fast failing agile company (according to taste), even if they can get the source it will be very hard to compile and run them. Reproducible builds is not exactly a solved problem.
  - y4mi 10y ago
    they need to put their entire environment into docker container and archive the images! theyll be able to recreate their whole environment at any time in the future! ...ill see myself out
  - ashitlerferad 10y ago
    > Reproducible builds is not exactly a solved problem. Indeed, but we are getting there (over 90% of packages from Debian stretch amd64 and 99.9% of OpenWRT packages): https://tests.reproducible-builds.org/debian/ https://tests.reproducible-builds.org/debian/ https://tests.reproducible-builds.org/openwrt/ https://tests.reproducible-builds.org/openwrt/

eloff 10y ago

DRAM does not have 1ns latency! On a 4ghz skylake chip you can access the L1 cache at 1ns. DRAM is going to be more in the range of 60(local)-100(remote) nanoseconds. Optane will likely be > 300ns latency from what I've heard, if you access it directly through the CPU memory controller via loads and stores, which is still very impressive.

nneonneo 10y ago
I'm quoting from the graph in the article. The numbers are also meant to be "on the order of", since the graph only provides that level of detail - so, for example, 1ns really means "1-9ns". I believe that they are using fairly best-case latency numbers, under the assumption that the memory accesses are close to sequential. For random memory accesses, as you note, the latencies are higher. Unfortunately the article doesn't go into detail on what Optane's worst-case latencies are, nor what the latencies will be like in a real functional system (mostly because Intel has only early prototypes to show).
- eloff 10y ago
  Yeah, I wouldn't do that, that graph is hardly accurate. 9ns won't get you a L3 cache hit on most skylake chips, nevermind main memory. For sequential access giving a latency number doesn't make sense - you need to talk throughput. You can get upwards of 20gb/s with a single core for DRAM. Here you're at least bounded by the 4x PCI interface (more likely the Optane device) so maybe 3GB/s if you're feeling generous.
chongli 10y ago
When we talk about 1ns latency for DRAM we aren't talking about access latency, we're talking about CAS latency[0]. This is how fast the DRAM actually works. It doesn't include the rest of the overhead between the time the data is sent over the bus and the time it's loaded into a register and ready for an instruction to operate on it. CAS latency for DDR3-3300 is less than 1/3ns, according to the article below. If Intel's new Optane memory can achieve addressing on the order of 10ns, it will be very competitive with DRAM, since all of other overhead along the data path ought to be similar. [0] https://en.wikipedia.org/wiki/CAS_latency https://en.wikipedia.org/wiki/CAS_latency

ChuckMcM 10y ago

Ok, a couple of things. First, I found it really amazing at how convoluted Intel plotted their numbers on that latency graph so that it would "Up and to the right" which everyone "knows" is good. The second thing is that Intel has been claiming multiple GB/second of throughput as well. They really do believe this will be a replacement for DRAM on some platforms. As in you read into your L3 case from this stuff and you flush to it when you write out a dirty cache lines. And while that will make the overall system slower, it gives it literally instant stop/start capability if the key parts of your architecture are static (can retain data at 0 clock). What that means is a laptop that can turn it self off between waiting for sectors to read in from the disk or packets to come off the network, or keys to be pressed by the user. Non-illuminated run times in days off of a battery source rather than hours. Imagine a 1.2TB of this stuff on the motherboard substituting for DRAM. So you've got every application and all the data for your applications already "in memory" as far as the chip is concerned. App switching? Instant, app data availability? instant. Quite a different experience than what we have today.

visarga 10y ago
> Quite a different experience than what we have today. For example, I only have to wait at most one second for an app to load, if it's not already open and minimized. It's comparable to the time it takes me to click a button. And my computer is rebooted only once every few months, so it's always up. This improvement will be more meaningful for random access database operations.
simula67 10y ago
Is this technology costly ? EDIT: Does not seem to be. “You could put the cost somewhere between NAND and DRAM. Cost per bit, it’s likely to be in between them somewhere. But actual cost will result from the products we bring to the marketplace.” http://hothardware.com/news/intel-and-micron-jointly-drop-disruptive-game-changing-3d-xpoint-cross-point-memory-1000x-faster-than-nand http://hothardware.com/news/intel-and-micron-jointly-drop-di...
sspiff 10y ago
> What that means is a laptop that can turn it self off between waiting for sectors to read in from the disk or packets to come off the network, or keys to be pressed by the user. Yeah, no. It might be able to turn of the CPU, but everything else would have to keep running. Graphics hardware does not deal well with frequent state changes. Network hardware would still need to run to keep its clock in sync with the signal. So, you get to turn off a handful of components, which is where we already are today - CPUs spend most of their time in deep sleep states. USB devices and chipsets implement sleep states. Graphics hardware clocks down significantly.

todd8 10y ago

To put these latency numbers in perspective 1ns is about 11 inches at the speed of light.

umanwizard 10y ago
Or three cycles on a typical desktop CPU.
- todd8 10y ago
  Yes, but even one round trip to the store could blow most of your latency budget. The store will have to be right next to the processor.

Unklejoe 10y ago

I wonder what the actual latency improvements will be. If it's connected through PCI express, there will be a lower limit which is dictated by the bus. While reducing the latency of the drive will still certainly matter, this latency introduced by the bus will serve to lessen the relative improvements with respect to SSDs. PCI Express is packetized and it takes a little over 1 nanosecond per byte for the 3.0 version. I believe the minimum packet size is 20 bytes, but I'm not positive on that. It seems like the latency could never be less than 2 * (1 * 20) nanoseconds in the case of a random access, and this is before the latency of the drive itself is factored in. Surely there will be a few clock cycles required for the drive HW to decode the PCIe transaction and act upon it. That being said, any latency improvement of the drive _will_ have a direct reduction in effective latency in the end, so it’s all good news to me. I’m just curious about the 1000x figure that’s being referenced everywhere.