4 ms·
Atomic part has to notify the rest of caches to invalidate the cache line. Local latency in the best case.
by xxs 10y ago
Atomic part has to notify the rest of caches to invalidate the cache line. Local latency in the best case.
- gpderetta 10y agoFYI, any store has to invalidate remote cachelines, that's taken care by the coherence protocol even before the store is actually performed. Memory barrier (and atomic operations) don't have anything to do with it.
- JoachimSchipper 10y agoWhether stores invalidate remote cachelines depends entirely on the architecture. But yes, Intel has fairly strong coherency.
- gpderetta 10y agoIt seems to me that any cache coherent system needs to do that. If multiple writers can be updating a cacheline a the same time [1] you can't talk of coherency at all. Intel is stronger as it guarantees a total ordering of modifications across all cachelines, but any coherent system will guarantee the ordering of modification of a single cacheline. [1] visibly at least. HTM complicates things a bit of course.
- imtringued 10y agoSo false sharing is the problem?
- gpderetta 10y agoIf the refcount is allocated in the same cacheline with the rest of the object, then false sharing is also a problem. But the violation of the single writer principle when updating refcounts is actually a form of true sharing.