4 ms·

One problem would be instruction size. On a system with (e.g.) 32 registers, each register can be addressed with 5 bits, while a memory address is 32-64 bits.

by panic 10y ago

bluetomcat 10y ago
There could be a scheme for encoding large immediates in a compact way, just like ARM does. Besides, I don't think that instruction size or instruction cache pressure is the bottleneck nowadays.
- cesarb 10y ago
  The RISC-V designers implemented a compressed instruction extension (the most common instructions can be represented in half the size), and found a performance gain. So yes, instruction size matters. From the 1.9 draft of the RISC-V compressed instructions specification: "Waterman shows that RVC fetches 25%-30% fewer instruction bits, which reduces instruction cache misses by 20%-25%, or roughly the same performance impact as doubling the instruction cache size." Larger caches are slower, so just doubling the cache size doesn't necessarily recover the performance lost by larger instructions.
  - userbinator 10y ago
    implemented a compressed instruction extension (the most common instructions can be represented in half the size), and found a performance gain. ...which makes me wonder why they didn't just make that the standard. x86 is dense and that's partly where its performance comes from.
    - cesarb 10y ago
      They planned for it since the beginning. While the base RISC-V encoding uses only 32-bit instructions, it's actually a variable-length encoding, where the least significant bits define the instruction length. If the least significant bits are 00, 01, or 10, it's a 16-bit instruction. The base RISC-V was designed to be minimal; for instance, hardware multiply and divide is the M extension. I expect that, once the C (compressed instructions) extension is standardized, most high-performance implementations will include it, since the extra area cost should be minimal compared to the out-of-order machinery; small in-order implementations where area is at a premium and performance is not so important will continue to use only the base 32-bit instructions. There's even a variant, RV32E, which omits half the registers to make the core even smaller.
    - _chris_ 10y ago
      x86 is NOT dense - it averages nearly 4 bytes per instruction on workloads such as SPEC. And not everybody wants to go through the design effort to support variable-length encoding (it's non-trivial and can potentially increase pipeline latency to support it). It very well could become a de facto RISC-V standard, but that remains to be seen.
    - __s 10y ago
      In the paper they discuss how x86 isn't even dense, & barely competes with ARM's constant width instructions
- marcosdumay 10y ago
  Well, if you really want to push it, you can have a smaller, faster L1 cache, like with 32 words or so, and a set of special instructions, shorter, but only capable of addressing this small memory space... Instruction fetching and parsing is an important bidimensional bottleneck that does restrict your architecture. It's not a bottleneck for run-time performance because it's predictable and optimized at design time.
meanduck 10y ago
Memory can addressed by taking offset from RSP (or [ 0x10 ] eg).
- bluetomcat 10y ago
  Here is how I implemented a small instruction set for the VM of my experimental language, without using GPRs. Basically, instruction operands are divided into 4 classes: - G (global): the operand refers to the global memory space and contains an offset and size. - A (automatic): the operand refers to the current stack frame. The offset is relative to the current base pointer. - I (immediate) - T (temporary): this is where intermediate results from computations are stored. For example, the result of `a + b` from `(a + b) * c` would be stored in the T memory space. Upon the end of a statement in the HLL, all values in the temporary space are discarded. Reference: https://github.com/bbu/quaint-lang/blob/master/src/exec.c https://github.com/bbu/quaint-lang/blob/master/src/exec.c
  - meanduck 10y ago
    > - A (automatic): the operand refers to the current stack frame. The offset is relative to the current base pointer. Did you mean stack pointer ? base pointer gets set once where as stack pointer changes between every function call. > Here is how I implemented a small instruction set for the VM of my experimental language, without using GPRs. stack pointer is still necessery unless some memory region is predefined as stack pointer. 'A class' can be made more space efficient by dividing stack into 16 chunks and then instruction would only need 4bit to address.
    - meanduck 10y ago
      According to the thesis recent intel microarchs caches the top several words of the stack[1]. Thesis references intel optmization manual but does not say where in the manual. [1] pg 12, para 5.

One problem would be instruction size. On a system with (e.g.) 32 registers, each register can be addressed with 5 bits, while a memory address is 32-64 bits.

by panic 10y ago

One problem would be instruction size. On a system with (e.g.) 32 registers, each register can be addressed with 5 bits, while a memory address is 32-64 bits.

bluetomcat 10y ago

There could be a scheme for encoding large immediates in a compact way, just like ARM does. Besides, I don't think that instruction size or instruction cache pressure is the bottleneck nowadays.

cesarb 10y ago
The RISC-V designers implemented a compressed instruction extension (the most common instructions can be represented in half the size), and found a performance gain. So yes, instruction size matters. From the 1.9 draft of the RISC-V compressed instructions specification: "Waterman shows that RVC fetches 25%-30% fewer instruction bits, which reduces instruction cache misses by 20%-25%, or roughly the same performance impact as doubling the instruction cache size." Larger caches are slower, so just doubling the cache size doesn't necessarily recover the performance lost by larger instructions.
- userbinator 10y ago
  implemented a compressed instruction extension (the most common instructions can be represented in half the size), and found a performance gain. ...which makes me wonder why they didn't just make that the standard. x86 is dense and that's partly where its performance comes from.
  - cesarb 10y ago
    They planned for it since the beginning. While the base RISC-V encoding uses only 32-bit instructions, it's actually a variable-length encoding, where the least significant bits define the instruction length. If the least significant bits are 00, 01, or 10, it's a 16-bit instruction. The base RISC-V was designed to be minimal; for instance, hardware multiply and divide is the M extension. I expect that, once the C (compressed instructions) extension is standardized, most high-performance implementations will include it, since the extra area cost should be minimal compared to the out-of-order machinery; small in-order implementations where area is at a premium and performance is not so important will continue to use only the base 32-bit instructions. There's even a variant, RV32E, which omits half the registers to make the core even smaller.
  - _chris_ 10y ago
    x86 is NOT dense - it averages nearly 4 bytes per instruction on workloads such as SPEC. And not everybody wants to go through the design effort to support variable-length encoding (it's non-trivial and can potentially increase pipeline latency to support it). It very well could become a de facto RISC-V standard, but that remains to be seen.
  - __s 10y ago
    In the paper they discuss how x86 isn't even dense, & barely competes with ARM's constant width instructions
marcosdumay 10y ago
Well, if you really want to push it, you can have a smaller, faster L1 cache, like with 32 words or so, and a set of special instructions, shorter, but only capable of addressing this small memory space... Instruction fetching and parsing is an important bidimensional bottleneck that does restrict your architecture. It's not a bottleneck for run-time performance because it's predictable and optimized at design time.

meanduck 10y ago

Memory can addressed by taking offset from RSP (or [ 0x10 ] eg).

bluetomcat 10y ago
Here is how I implemented a small instruction set for the VM of my experimental language, without using GPRs. Basically, instruction operands are divided into 4 classes: - G (global): the operand refers to the global memory space and contains an offset and size. - A (automatic): the operand refers to the current stack frame. The offset is relative to the current base pointer. - I (immediate) - T (temporary): this is where intermediate results from computations are stored. For example, the result of `a + b` from `(a + b) * c` would be stored in the T memory space. Upon the end of a statement in the HLL, all values in the temporary space are discarded. Reference: https://github.com/bbu/quaint-lang/blob/master/src/exec.c https://github.com/bbu/quaint-lang/blob/master/src/exec.c
- meanduck 10y ago
  > - A (automatic): the operand refers to the current stack frame. The offset is relative to the current base pointer. Did you mean stack pointer ? base pointer gets set once where as stack pointer changes between every function call. > Here is how I implemented a small instruction set for the VM of my experimental language, without using GPRs. stack pointer is still necessery unless some memory region is predefined as stack pointer. 'A class' can be made more space efficient by dividing stack into 16 chunks and then instruction would only need 4bit to address.
  - meanduck 10y ago
    According to the thesis recent intel microarchs caches the top several words of the stack[1]. Thesis references intel optmization manual but does not say where in the manual. [1] pg 12, para 5.