4 ms·
Three pre-cooked DDR controller macro blocks. Now think of how many soft controllers can be added with so many spare pins. Also, think of all the high-speed tr
by sklogic 11y ago
Three pre-cooked DDR controller macro blocks. Now think of how many soft controllers can be added with so many spare pins.
Also, think of all the high-speed tranceivers to feed the data into an FPGA.
For the problems I am working with, FPGAs, even the mid-range ones, are far more suitable than the top GPUs.
- adwn 11y agoThere are no hard-core SDRAM controllers on the KU040, I'm talking about soft-core controller. The bandwidth is limited by the number of IO pins (what good is a memory controller without access to a memory chip?); SDRAM needs quite a number of signal lines. What FPGA device are you using? How many memory controllers are on it, what width do they have, and at what frequency are the memory modules operating? What external bandwidth do you actually achieve? > For the problems I am working with, FPGAs, even the mid-range ones, are far more suitable than the top GPUs. I believe you, but we're talking about maximum external memory bandwidth, not suitability in general.
- sklogic 11y agoTbh I do not care that much about the external memory bandwidth, I only need internal plus some slow swapping into external DDR (used at most 4 channels so far) - my use cases are solely streaming, therefore tranceivers are more than enough. In some cases even a lowly Spartan6 is able to beat all the shit out of Teslas. Compare hundreds of memory fetches a cycle vs. whatever the pitiful NVidia cache is capable of (and remember that if your load is trashing your cache, you're screwed, no way to fix it if there is no option to pre-scramble your data for a linear access).
- sitkack 11y agoExternal bandwidth is, this isn't going to change. The fpga will have full access to caches, this is where it will shine.