> As dies get bigger, there's no law of nature saying that CPU power must be concentrated far from memory. Actually, there is. The main reason why the L1 cache

> As dies get bigger, there's no law of nature saying that CPU power must be concentrated far from memory. Actually, there is. The main reason why the L1 cache is so small, is that a larger cache would take more cycles to access. The L2 cache is allowed to have a higher latency, so the electrical signals have more time to propagate through a physically larger area. 3D stacked dies alleviate this problem, and the trend goes towards putting several dies side-by-side in a single package (a chip), enabling lower latencies, higher throughput, and less power consumption.