4 ms·
ARM isn't open sourcing anything anytime soon. Take a look at OpenRISC and RISC-V. They're aiming at a fully open source SoC implementation in silicon. http://
by mafuyu 11y ago
ARM isn't open sourcing anything anytime soon. Take a look at OpenRISC and RISC-V. They're aiming at a fully open source SoC implementation in silicon.
http://openrisc.io/ http://openrisc.io/
http://riscv.org/ http://riscv.org/
- agumonkey 11y agoBut IIRC (some blog benchmark) they are very very slow.
- zhemao 11y ago(Disclaimer: I am a PhD student in the Berkeley computer architecture group, which designs RISC-V) An ISA can't be "fast" or "slow". It's just a specification. There's no reason you can't build a RISC-V core that's just as fast as an ARM or x86 core. The only reason we haven't done so is because we don't have access to the modern fabrication technologies that Intel and commercial ARM licensees use.
- theresistor 11y agoInstruction sets very much can be fast or slow, at least in the context of discussing specific use cases. Many of the inner loops that take up most of the active cycles on a CPU today (crypto, compression, imaging, signal processing, linear algebra) have very specific code patterns that are can be targeted with specialized instructions that provide integer-multiple reductions in instruction count. Let's assume that application-targeted instructions can reduce the size of the inner loops in these applications by 2x. Even the RISCiest cores do not, in practice, run at 2x the clock speed or 2x the issue rate of cores with application-targeted instructions. Thus, ISAs with baked in support for these use-case accelerating instructions will be more performant. The RISCy core probably wins on mm^2, but a perf/mm^2 analysis will be highly dependent on how well designed the application-specific instructions are for area conservation.
- zhemao 11y agoOkay, fair enough. What you describe are essentially extended instructions, and RISC-V has support for it. One of our teams is currently working on a vector co-processor that can get very good performance on compute-heavy workloads.
- zhemao 11y agoAlso, the benchmarks we did a while ago on a taped-out chip with our in-order RV64 core, Rocket, showed that it compared quite favorably to an ARM Cortex A5. http://riscv.org/download.html#tab_rocket_core http://riscv.org/download.html#tab_rocket_core Unfortunately, it would be quite difficult for outside organizations to replicate these measurements unless they can pay TSMC for a fab run.
- smcl 11y agoAlternatively there's the Open Processor Foundation, who are taking advantage of the fact that Hitachi's SuperH patents are lapsing over the next few years (some already have): http://0pf.org/about-ocf.html http://0pf.org/about-ocf.html The official website above has a lot of info, but there is a nicer intro @ lwn: https://lwn.net/Articles/647636/ https://lwn.net/Articles/647636/
- renox 11y agoI really wonder what is the point of OpenRISC/RISC-V, isn't there already open SPARC? I know that they removed quite a lot of things (too much IMHO) in the RISC-V ISA to reduce the number of gates needed, but this has a price: there is probably much more support for SPARC in compilers/applications than for RISC-V.
- joezydeco 11y agoI know. I was trying to be subtly sarcastic (and obviously failed).