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Don't we already hit that on GPUs? Or do they only have shared caches?
by creshal 11y ago
Don't we already hit that on GPUs? Or do they only have shared caches?
- varelse 11y agoGPUs aren't cache-coherent yet. That said, they have fantastic atomic ops performance relative to CPUs. I'd guess that the lack of performance benefit so far is because it's possible to write many algorithms with the assumption that there is no cache coherency.
- robmccoll 11y agoTheir atomic operations used to be extremely costly from a utilization perspective. They would shut down all other threads in a warp while the thread performing the atomic ran alone. Is that still the case?
- varelse 11y agoFixed as of Maxwell to the best of my knowledge. But even then, I found them more efficient for reduction operations in global memory than any other method (using fixed-point math for places where a deterministic sum was required).
- seanmcdirmid 11y agoI'm not really a GPU person, but my understanding is that GPUs have very simple memory models, memory reads and writes are scheduled more manually. But this is part of their appeal, why they can run so fast, but also why they aren't as general as CPUs. But my knowledge is a bit out of date, since GPUs are actually including caches now, and what they can do seems to evolve rapidly.
- ajross 11y agoYeah, the traditional GPU usage is a streaming thing. Textures are read only, vertex and fragment data is either output-only or input-only depending on shader type. The only R/W memory requiring synchronization is the framebuffer, which is handled by specialized hardware anyway.
- robmccoll 11y agoKind of, you get the experience of coherent access from a software perspective. http://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_fermi_compute_architecture_whitepaper.pdf
- seanmcdirmid 11y agoJust a formatting note: if you could remove the verbatim space before the url, HN would recognize it as one.
- MaulingMonkey 11y agohttp://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_fermi_compute_architecture_whitepaper.pdf http://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_...
- btown 11y agoIntel's Xeon Phi architecture has 60+ cores with multiple threads each, with cache coherence (albeit using a more standard dictionary): http://htor.inf.ethz.ch/publications/img/ramos-hoefler-cc-modeling.pdf http://htor.inf.ethz.ch/publications/img/ramos-hoefler-cc-mo... - so we're getting there.
- ajross 11y agoYes, though IIRC they had to modify the long-standing IA memory ordering rules in order to make that happen. Xeon Phi requires manual fence management in most cases, I believe.
- seanmcdirmid 11y agoNote that those particular cores are also doing SIMT like GPUs are, so the problem is different from cache coherence on general purpose cores.