6 ms·

I like the factual tone of the article and specifically the fact that it honestly mentions that there has been no practical performance benefit yet in benchmark

• seanmcdirmid 11y ago
  The benefit is obvious in book keeping space overhead for the shared cache as the number of core rise. This could be very useful when/if we ever hit 256 cores per CPU. The technique kind of reminds me of Jefferson's virtual time (and time warp), which rather exists in a distributed simulation context. Virtualizing time to manage coherence of reads and writes is a very good idea.
  • creshal 11y ago
    Don't we already hit that on GPUs? Or do they only have shared caches?
    • varelse 11y ago
      GPUs aren't cache-coherent yet. That said, they have fantastic atomic ops performance relative to CPUs. I'd guess that the lack of performance benefit so far is because it's possible to write many algorithms with the assumption that there is no cache coherency.
      • robmccoll 11y ago
        Their atomic operations used to be extremely costly from a utilization perspective. They would shut down all other threads in a warp while the thread performing the atomic ran alone. Is that still the case?
        • varelse 11y ago
          Fixed as of Maxwell to the best of my knowledge. But even then, I found them more efficient for reduction operations in global memory than any other method (using fixed-point math for places where a deterministic sum was required).
    • seanmcdirmid 11y ago
      I'm not really a GPU person, but my understanding is that GPUs have very simple memory models, memory reads and writes are scheduled more manually. But this is part of their appeal, why they can run so fast, but also why they aren't as general as CPUs. But my knowledge is a bit out of date, since GPUs are actually including caches now, and what they can do seems to evolve rapidly.
      • ajross 11y ago
        Yeah, the traditional GPU usage is a streaming thing. Textures are read only, vertex and fragment data is either output-only or input-only depending on shader type. The only R/W memory requiring synchronization is the framebuffer, which is handled by specialized hardware anyway.
    • robmccoll 11y ago
      Kind of, you get the experience of coherent access from a software perspective. http://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_fermi_compute_architecture_whitepaper.pdf
      • seanmcdirmid 11y ago
        Just a formatting note: if you could remove the verbatim space before the url, HN would recognize it as one.
        • MaulingMonkey 11y ago
          http://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_fermi_compute_architecture_whitepaper.pdf http://www.nvidia.com/content/pdf/fermi_white_papers/nvidia_...
    • btown 11y ago
      Intel's Xeon Phi architecture has 60+ cores with multiple threads each, with cache coherence (albeit using a more standard dictionary): http://htor.inf.ethz.ch/publications/img/ramos-hoefler-cc-modeling.pdf http://htor.inf.ethz.ch/publications/img/ramos-hoefler-cc-mo... - so we're getting there.
      • ajross 11y ago
        Yes, though IIRC they had to modify the long-standing IA memory ordering rules in order to make that happen. Xeon Phi requires manual fence management in most cases, I believe.
      • seanmcdirmid 11y ago
        Note that those particular cores are also doing SIMT like GPUs are, so the problem is different from cache coherence on general purpose cores.
• langarto 11y ago
  Well, the title is not very factual nor honest. It is completely hyperbolic. The idea looks interesting (I have not yet read the actual paper), but calling it «The first new coherence mechanism in 30 years» is ridiculous.
  • Anderkent 11y ago
    What other innovations in cache coherency handling have been created in the last 30 years?
    • scott_s 11y ago
      I'm not an architecture researcher, so I can't say from first-hand knowledge. But looking at the titles from the papers in the previous years of the conference that this paper is published in, Parallel Architectures and Compilation Techniques, would be a good start: http://dl.acm.org/event.cfm?id=RE206 http://dl.acm.org/event.cfm?id=RE206
    • langarto 11y ago
      As scott_s says, you could start looking at the papers presented in PACT in the last years (not all are about coherence, but there are a few almost every year). You should also look at ISCA and HPCA. In fact, you could start by looking at the Related Work section of this paper itself. The version at https://people.csail.mit.edu/devadas/pubs/tardis.pdf https://people.csail.mit.edu/devadas/pubs/tardis.pdf is better. It is quite telling that the paper does not make the outrageous claim of the title of MIT's press release. O(log N) of memory overhead per block is nothing new. There were commercial systems in the 1990s that achieved that (search for SCI coherence). Note that there are other overheads to consider (notably latency and traffic). This paper is very interesting and looks sound, but MIT's press release makes it look silly. Excuse me for not even trying to make a summary of the last 30 years of research in this field.
    • asb 11y ago
      DeNovo is worth a read: http://rsim.cs.illinois.edu/denovo/index.html http://rsim.cs.illinois.edu/denovo/index.html