zeusk

13 ms·

151.
by zeusk 3y ago
Also seems funny that author does not actually have first-hand experience of working or managing folks at Apple.
152.
by zeusk 3y ago
As you note in your edit; we already have to watch for that pitfall :) so really the best way out is to be as verbose as possible imo; a = a + c or auto nodep = *nodepp; nodep->next; Compilers and compute performance have grown to make t
153.
by zeusk 3y ago
But they could've fixed that by going a=(*p) and a=(-b); Kind of how we use (*p)->next instead of *p->next where p is node_t**
154.
by zeusk 3y ago
I worked at MS for 3 years after undergrad, My first year was 221k, 180k, 191k and would've been ~185k for Y4 then 160k after cliff. SSA is Special Stock Award given arbitrarily (M2s are not sure or have any say in who/how much to
155.
by zeusk 3y ago
Quickly being, 1 year and can go lower after 3 years if you don't get a SSA.
156.
by zeusk 3y ago
It quickly decays to around 150-180k; the refreshers and bonus are lousy <L63 at MSFT.
157.
by zeusk 3y ago
it isn't for you solely/exclusively. If it "improves" the service for everyone - that includes "you".
158.
by zeusk 3y ago
cacio e pepe; easily the best pasta dish vs effort imo.
159.
by zeusk 3y ago
He probably works on Google search or Pinterest. I want least engagement with the search engine; it's a fail if I'm spending time just looking at search page and not the results.
160.
by zeusk 3y ago
Pinterest is absolutely the worst; most of the time the linked page doesn't even have what I was looking for.
161.
by zeusk 3y ago
Yup; well that's because Microsoft has extremely high bar for backporting feature requests. In thread director's case, the missing functionality isn't a deal breaker for the types of systems restricted to Win 10.
162.
by zeusk 3y ago
1, is incorrect in the last paragraph about Intel Thread Director. The hardware classifies every thread context into one of 4 classes and provides the OS with dynamic perf/power values for all cores. It's the Windows thread schedu
163.
by zeusk 3y ago
Did apple ever have eGPU support? and even if they did, they had a nasty fallout with nvidia some time ago.
164.
by zeusk 3y ago
So a Mixture of Experts model; but then isn't ChatGPT using that already? Why're the models so bad at math despite being trained on academic papers and books clearly - or why do they hallucinate and make up non-existing citations?
165.
by zeusk 3y ago
How do you call C API from python? Through executable + stdin/stdout?
166.
by zeusk 3y ago
I̵t̵'̵s̵ ̵n̵o̵t̵ ̵a̵b̵o̵u̵t̵ ̵L̵D̵_̵P̵R̵E̵L̵O̵A̵D̵;̵ ̵m̵o̵r̵e̵ ̵l̵i̵k̵e̵ ̵y̵o̵u̵'̵r̵e̵ ̵c̵a̵l̵l̵i̵n̵g̵ ̵c̵l̵o̵n̵e̵ ̵i̵n̵ ̵p̵y̵t̵h̵o̵n̵ ̵p̵r̵o̵c̵e̵s̵s̵ ̵a̵n̵d̵ ̵t̵h̵e̵ ̵p̵r̵o̵c̵e̵s̵s̵ ̵a̵l̵r̵e̵a̵d̵y̵ ̵h̵a̵s̵ ̵t̵c̵m̵a̵l̵l̵o̵c̵ ̵o̵v̵
167.
by zeusk 3y ago
Software Engineer position is filled? Only the electrical engineer position is visible on the careers page.
168.
by zeusk 3y ago
Do all positions require USC (requirement for Active security clearance) or is "US Person" status (which includes LPR/GC holders) enough?
169.
by zeusk 3y ago
ASID (Address Space ID) or as Intel calls it PCID (Process Context ID). The OS juggles these based on what processes are resident on CPU and the various active mappings then uses INVPCID[0] during a context switch. [0]: https://w
170.
by zeusk 3y ago
It's unrelated to TLB; page table contention is related to associative caches where you can have two distinct addresses map to the same cache set and cause false cache miss or exhaust the cache set and cause repeated fill from memory.
171.
by zeusk 3y ago
If a CPU's caches are physically tagged and both process's page tables share the same backing physical page then the CPU will let the cache contents be used by either process as long as the OS doesn't explicitly flush/in
172.
by zeusk 3y ago
Email spam is implicitly solicited. You open your email knowing people are sending you spam. If you don't like it, you can stop opening your email and no more spam.
173.
by zeusk 3y ago
> Alder Lake has its AVX-512 disabled Alder lake has AVX-512 disabled because 512 bit data paths on atom cores don't make sense and Microsoft couldn't execute on a IHV specific scheduling change so quickly. AVX2+ and later Wind
174.
by zeusk 3y ago
Because it's not rational to pay $4000+ rent for 1 bed apartment regardless of how much you're paid; especially when that job has no reason to require a physical commute to a shared office space.
175.
by zeusk 3y ago
This whole idea is stupid. How about giving proper financial support for unfortunate and beaten down people and covering all expenses for sustaining life and not just give away money to lazy parents who don't want to work and contribut
176.
by zeusk 3y ago
I'm not just linking it as a proof, I now work at Intel and collaborate with Microsoft on bringing new platform technologies to life. I'm currently involved in VNNI and hybrid core scheduling KPIs. OpenVINO allows developers to ta
177.
by zeusk 3y ago
CPUs are actually involved, especially with SIMD like AVX and VNNI instructions. It all depends on the scale of your compute. https://www.intel.com/content/www/us/en/developer/tools/open...
178.
by zeusk 3y ago
Parent discovers the difference between DMA and RDMA
179.
by zeusk 3y ago
How do you attach kd to VM? While I was at MS, it was such a big PITA - we just had a bunch of IT managed machines with KVM console access and KDNET for debugging.
180.
by zeusk 3y ago
This looks pretty good! Hope you guys succeed.

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