yvdriess

6 ms·

91.
by yvdriess 1y ago
In defense of the OP: bump allocators are part of the CPython runtime. It's used to avoid calling malloc a bazillion times a second. Of course, it still needs to defer to libc for certain objects and to grab more memory for its pools&#
92.
by yvdriess 1y ago
Thanks for that article by the way. I've referenced it often to make the point that allocation behaviour is complex and messy. > I don’t believe this in even the slightest. That is not a meaningful metric for literally any actual wo
93.
by yvdriess 1y ago
Their pictoral representation is a "shut up and calculate" notation, you can always map it 1:1 with the linear algebra formulation. It was developed as a better tool of thought for working out proofs in QC. I had the pleasure of i
94.
by yvdriess 1y ago
Yes but those transistors moved to greener pastures.
95.
by yvdriess 2y ago
It is interesting to contrast Notch's arc with Zach Barth's, if you are familiar with the Infiniminer[1] connection. The latter has continued to make small idiosyncratic games with a small team and following his own interests. [1]
96.
by yvdriess 2y ago
Agreed, Intel needs to win back customers. Removing the MBA-staple strategy of artificial market segmentation would be a strong signal that they are serious about becoming an actual customer-first company.
97.
by yvdriess 2y ago
Some counter points. On the die size argument, which I see being echoed a lot online: Why would a customer care or factor that into their purchasing decisions? Saying that these dGPUs with large dies are what is going to put Intel out of bu
98.
by yvdriess 2y ago
True, but it depends on what you mean with fitting in memory. Succinct datastructures are used in genomics (e.g. bwa, megahit exome sequencer) because N is so large that you're actually hitting asymptotic behavior. For memory latency i
99.
by yvdriess 2y ago
That's because the OP is linking to the quickstart guide. There are benchmark numbers on the github's root page, but it does not appear to include the new deepseek yet: https://github.com/intel/ipex-llm/t
100.
by yvdriess 2y ago
Can confirm. I experienced EU EC research project red tape to similar than DARPA. Most of the red tape comes from excesses or abuses from the past. Government agencies tend to slap an extra layer of rules every time the grant money is being
101.
by yvdriess 2y ago
If you love the sound of the Floppotron, chiptunes and metal, I can heartily recommend Master Boot Record. https://masterbootrecord.bandcamp.com/album/hardwarez https://soundcloud.com/masterbootrecordmu
102.
by yvdriess 2y ago
Any concurrent GC will have an unpredictable impact on application threads. The more obvious is the necessary synchronization on GC startup and shutdown, e.g. to turn on write barriers during GC. Less obvious but perhaps more impactful is t
103.
by yvdriess 2y ago
Go GC's stop the world pauses are essentially synchronization barriers at the start and end of a GC phase. That pause length is a function of the number of worker threads, not the size of the heap. You can check this yourself by runnin
104.
by yvdriess 2y ago
Yep, it's an area denial weapon. You basically cannot do anything worthwhile in this space without violating someone's patents. It's beneficial patent and corporate lawyers, but it's detrimental to innovation. As an engi
105.
by yvdriess 2y ago
I agree that fuel cost and tax are not the reason trucks are so popular in the US. The main incentive for US manufacturers to have a large demand for light trucks because of the chicken tax. https://en.wikipedia.org/wiki&#x2
106.
by yvdriess 2y ago
PCIe 4.0 16x https://www.intel.com/content/www/us/en/products/sku/227961/...
107.
by yvdriess 2y ago
For the consumer GPUs, PCIe 4.0 x16 has plenty of BW headroom. The full sized x16 is more for stability reasons. Some vendors even put a couple of M.2 slots on PCI4/5 GPU board to recuperate the unused PCIe lanes.
108.
by yvdriess 2y ago
It's not the size of the technical insight that matters, it's what you know what do with it. Point being, a smart and capable CEO can still have misaligned incentives (read: optimize for personal benefit).
109.
by yvdriess 2y ago
In defense of the chip designers: Design pipelines are deep and Intel at the time famously had very node-specific designs without industry-standard PDKs. The moment engineers were told to switch a design to 14nm, it basically reset the 5 ye
110.
by yvdriess 2y ago
It does help to retain the talent, those 5-10y engineers have a house on mortgage and need a higher pay incentive to uproot their lives. At least, that was probably the reasoning before, things have changed: - WFH means you do not even have
111.
by yvdriess 2y ago
In short, timing-attack computed?
112.
by yvdriess 2y ago
To add to that, AMD's has the more lucrative higher-margin part of that market.
113.
by yvdriess 2y ago
Even without the patents, there is a lot in x86 and it would take an order of magnitude more engineers to make a compatible x86 CPU than a RISCV with standard extensions.
114.
by yvdriess 2y ago
Over here in the real world of bottom 10% firing company cultures: those top engineers are leaving the company because they are tired of the culture of infighting and backstabbing, because setting up to others to fail and blaming them is ju
115.
by yvdriess 2y ago
Control flow and data flow of programs are modelled as graphs so that certain analysis and transformations can be applied. That involves subgraph similarities, graph searches, graph transformation rules etc. And at the tail end, register al
116.
by yvdriess 2y ago
Yep! I used BrookGPU for my GPGPU master thesis, before CUDA was a thing. AMD lacked followthrough on yhe software side as you said, but a big factor was also NV handing out GPUs to researchers.
117.
by yvdriess 2y ago
somethingawful
118.
by yvdriess 2y ago
That's true when you compare electrical vs optical links for NICs in datacenters. But this is about Silcon Photonics, which changes the equation significantly. e.g. it can be used for on-chip optical interconnects. The silicon real est
119.
by yvdriess 2y ago
Just before Epiphany, there was also the Tilera, which had a lot in common with the Transputer. Our lab got one and we played around with it, but it was a pain to program. Transputer had OCCAM, Tilera chased after the C model and shared coh
120.
by yvdriess 3y ago
Saying this as a big hardware atomics enjoyer: Static atomic variables are not fast, are not parallel and definitely are the worst kind of cache misses. Atomics are also atomic only on that one single operation, such as manipulating a singl

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