yvdriess

43 ms·

571.
by yvdriess 15y ago
I meant bad for the entire Tilera processor. I haven't found any SPEC results for a Tilera processor, but we've been experimenting with a TilePro64 in out research lab for a while: http://soft.vub.ac.be/~smarr/2010/11/roarvm-the-manycore
572.
by yvdriess 15y ago
How would you compare its performance? It would do really bad on the SPEC benchmarks for example. Some parallel algorithms would do well on Tilera. If not in absolute speed, at least in FLOPS/Watt
573.
by yvdriess 15y ago
The mass production of transistors is completely thanks to its relatively etching process. I wonder if we will see a relatively similar process for alternative transistor technology.
574.
by yvdriess 15y ago
Reminded me of another super-coder: http://en.wikipedia.org/wiki/Fabrice_Bellard
575.
by yvdriess 15y ago
You never miss keypads ... until you want to play a roguelike.
576.
by yvdriess 15y ago
Cliff Click's presentation on the subject are quite enlightening. Although, Azul's hardware and target are quite different from the 1000-core tilera idea. I doubt it is a counterpoint to Ungar's message.
577.
by yvdriess 15y ago
The Tilera architecture is different enough to make that benchmark meaningless though. You have to compare the best algorithm for one architecture with the best for the other. Of course, you could be right if that bag of tricks they opene
578.
by yvdriess 15y ago
You might be interested in this presentation on running an internet community: http://vimeo.com/5623703
579.
by yvdriess 15y ago
Well I learned something new. SBCL and CLISP seem to have good unicode support that work well with emacs+slime.
580.
by yvdriess 15y ago
What is this sudden feeling? It is like a thousand HN readers cringed simultaneously.
581.
by yvdriess 15y ago
> SICP is dated and doesn't really match what modern languages can do. You really need to elaborate on that. Especially given how Guido could have used reading SICP when implementing Python and how Brendon was thoroughly inspired by Sc
582.
by yvdriess 15y ago
Indeed, that is the only correct use of Design Patterns.
583.
by yvdriess 15y ago
Out of curiosity, how did they typeset those mathematical formulae? Still by carefully tiling little metal blocks or with something more advanced.
584.
by yvdriess 15y ago
You'll get an extra factor of perfomance if you do a (loop for rand across *nums* summing rand) instead of using the generic reduce.
585.
by yvdriess 15y ago
> There's no TCO in the C standard. That doesn't make tail-recursive C programs any less correct.
586.
by yvdriess 15y ago
I just want to point out that the RISC/CISC term is anachronistic, it doesn't really apply anymore to the desktop and server world. Intel's x86 processors are RISC micro-instructions but with a CISC-like interface for example, effectively
587.
by yvdriess 15y ago
Or as some would tell you: Bitcoins are backed by gold. Comedy gold.
588.
by yvdriess 15y ago
Special keynote lecture by Bill Cosby?
589.
by yvdriess 15y ago
Hey, want to click my cow?
590.
by yvdriess 15y ago
And here is the guy's Something Awful thread: http://forums.somethingawful.com/showthread.php?threadid=343...
591.
by yvdriess 15y ago
It appears that it just scans source files, not actual key presses. I barely touch the parenthesis keys when programming Lisp for example.
592.
by yvdriess 15y ago
Is there any relation between Inmos and Tilera? They basically revived the full transputer.
593.
by yvdriess 15y ago
Then let's agree to agree. :)
594.
by yvdriess 15y ago
You are right because the current hardware is biased towards sequential computation where threads&locks are the most efficient. This gives rise to situations where a handful of specialists work years on giving you that one lockless que
595.
by yvdriess 15y ago
Dataflow means a language or machine who's execution is driven by the availability of data. In a dataflow computational model you do not have the concept of memory. In a Von Neumann architecture (viz. your current CPU) execution is determi
596.
by yvdriess 15y ago
a) They have, ATI implemented Brook+ b) GPUs are still first and foremost special purpose hardware. Few applications are benefitting from moving all your data over to your graphics memory, pushing it through a broad but slow pipe and copyin
597.
by yvdriess 15y ago
Agreed, the cost is shifted to the back-end. But sometimes it is worth to pay that cost up-front, cfr the memory management debate. Synchronization and concurrency are much simpler in a system where you do have guarantees. No amount of inte
598.
by yvdriess 15y ago
Dataflow architectures and languages for example. Or even vanilla SIMD instructions. The heart of the issue is that von-Neumann architectures are really not well suited to doing parallel programming: global PC in a single random access read