wtallis

31 ms·

691.
by wtallis 1y ago
Traceability of transactions doesn't seem at all related to the issue at hand.
692.
by wtallis 1y ago
Your last sentence does not follow from the preceding one. Hybrid drives were doomed by having truly tiny caches, making them not particularly fast (you need a lot of flash chips in parallel to get high throughput), prone to cache thrashing
693.
by wtallis 1y ago
Given Intel's history of being in denial about their troubles (in spite of the apparent risk of investor lawsuits), them suggesting they might cancel 14A and beyond should be taken seriously. That statement could just as easily be th
694.
by wtallis 1y ago
> The elected branches don’t have a “mother may I” relationship with the courts. That "mother may I" phrase implies asking for pre-approval for routine stuff, which obviously isn't what's at issue here. > Injuncti
695.
by wtallis 1y ago
> Live by the sword, die by the sword. I'm not seeing how that applies. There's a clear asymmetry between lower courts issuing temporary restraining orders and preliminary injunctions on the basis of well-established preced
696.
by wtallis 1y ago
If Intel's fabs has been spun out and operating at arms length from Intel's chip design side, then Intel's fabs would be dead . The guaranteed volume from manufacturing Intel's CPUs is all that's been keeping their
697.
by wtallis 1y ago
The point is that AMD didn't really go fabless in 2009. They didn't own the fab anymore but were still tied to it, so they were not free to exercise the number one advantage of being fabless until much later.
698.
by wtallis 1y ago
Why is the asymmetry a show-stopper for you? It would seem like having lots of E-cores would be advantageous for compiling, and still having some P-cores means you don't lose performance when linking.
699.
by wtallis 1y ago
The Pentium 3 is what eventually topped out at 1.4 GHz, for the 130nm Tualatin parts introduced in 2001. The Pentium 4 started at 1.4GHz and 1.5GHz with the 180nm Willamette parts introduced in 2000. Those were eventually released wit
700.
by wtallis 1y ago
Looking at GitHub is probably significantly undersampling the kinds of C projects that would be doing static linking, many of which pre-date GitHub.
701.
by wtallis 1y ago
> and may-or-may-not end up in the same original thread That sounds like a problem stemming entirely from a decision to share a ring among multiple application threads. Is there a good reason to do so? Each thread that needs to do IO can
702.
by wtallis 1y ago
You can also directly link submitted operations into a chain that will be executed in-order but without ordering dependencies on other operations not submitted as part of the chain.
703.
by wtallis 1y ago
Peltier coolers have non-zero thermal conductivity and are pretty thin. At some point, heat leakage from the hot side to the cool side catches up to the rate of heat removal the cooler is capable of. What that point is will vary between dev
704.
by wtallis 1y ago
If your "cost per transistor" calculation includes amortization of the fixed costs of taping out a chip, over the expected production volume, then you can sometimes genuinely end up with newer process nodes being more expensive. D
705.
by wtallis 1y ago
You don't need to start spawning new threads to use io_uring as a backend for synchronous IO APIs. You just need to set up the rings once, then when the program does an fwrite or whatever, that gets implemented as sending a submission
706.
by wtallis 1y ago
Most of the security concerns with io_uring that I've seen aren't related to the shared buffers at all but simply stem from the fact that io_uring is a mechanism to instruct the kernel to do stuff without making system calls , so
707.
by wtallis 1y ago
The on-die ECC used by DDR5 (and pretty much all other recent DRAM) actually doesn't have many compatibility implications, precisely because it's done entirely on-die unlike traditional ECC memory modules that include an extra one
708.
by wtallis 1y ago
You seem to be saying that chasing fashion could be a sufficient justification for UI churn, instead of acknowledging that it will only ever be a very weak factor at best in favor of redesign, and never enough on its own to overcome the u
709.
by wtallis 1y ago
Pretending that aesthetics can be completely separated from usability is wrong, and only benefits the overzealous designers who need to be restrained.
710.
by wtallis 1y ago
I'm going to assume you don't want Excel to look the same on your desktop as on your phone. But even between Windows and macOS, I find it hard to believe you don't want at least a reasonable baseline of appropriate native beh
711.
by wtallis 1y ago
Consider the simple case on a desktop OS of how to arrange the "OK" and "Cancel" buttons on a dialog box. For an experienced user of the platform, it doesn't actually matter at all how legible your button labels are
712.
by wtallis 1y ago
> solves the same problem set with the same or better performance The games industry has spent the last decade adopting techniques that misleadingly inflate the simple, easily-quantified metrics of FPS and resolution, by sacrificing qua
713.
by wtallis 1y ago
On a phone, it can be tempting for an app developer to approach design as if their app is temporarily taking over the phone and transforming the entire device into the custom gadget your app embodies, since the app's UI will be filli
714.
by wtallis 1y ago
The problem is this mindset that constant UI churn chasing "fashion" could ever be purely superficial and harmless. You say people would grow bored with a UI that never changes, but on the other hand, people learn to use a UI
715.
by wtallis 1y ago
It's a management failure. Either management is directly approving gratuitous UI redesigns, or they're making the mistake of giving designers unrestrained freedom to decide what UI changes ship.
716.
by wtallis 1y ago
I think "sales" is just one of the post-hoc rationalizations. The real purpose very often is simply to justify the money you spent on UI designers; there's a kind of sunk cost fallacy where spending resources exploring design
717.
by wtallis 1y ago
Their Grace datacenter CPU is basically a chip where they put down all the LPDDR5 memory controllers (albeit curiously slow), NVLINK and PCIe IOs they needed around the perimeter, and then filled in the interior with boring off the shelf AR
718.
by wtallis 1y ago
Intel added PREFETCHW to their Broadwell processors launched in 2014, years after AMD dropped all 3DNow! instructions except the prefetch instructions. That timeline strongly suggests that the instructions aren't no-ops and likely are
719.
by wtallis 1y ago
Do you mean storing the next index/offset and having the pointer value calculated as late as possible by adding the starting address (and maybe multiplying the index by sizeof)? That would probably defeat/mislead Intel's pr
720.
by wtallis 1y ago
Please do me the courtesy of not misrepresenting what I have said and clarified. I have not said that AndroidAPS or Loop or any other DIY medical device software is stupid. I have only said that it is something a reputable business woul

More ›