wtallis

5 ms·

31.
by wtallis 2mo ago
It doesn't really do much in the way of processing ( https://www.siliconmotion.com/download/3PS/a/SM750_PB_EN_201... ); it's pretty much just a dumb framebuffer. You can wire it up to output over an
32.
by wtallis 2mo ago
You cannot directly inspect the degree of fragmentation, because it has less to do with being contiguous in the Logical Block Address (LBA) space and more to do with having been written at the same time. To properly defragment a file on a S
33.
by wtallis 2mo ago
In case you haven't been paying attention, DRAM and NAND are also pretty expensive these days, relative to where they were a year ago. The drastically different scaling trends for logic and SRAM on the same die are important, but I&#x2
34.
by wtallis 2mo ago
I'm going to ignore the first half of your comment, because it really only serves to disclose the limits of your knowledge. The problem with your rambling and speculation is that you're not making any attempt to think about what c
35.
by wtallis 2mo ago
I wonder if we might eventually see stacking of NAND, logic, and DRAM dies together so each can still be fabbed on their specialized process. Getting all three on one wafer is extremely impractical, but having them all connected with TSVs o
36.
by wtallis 2mo ago
You seem to think that "compute in memory" would mean the disappearance of commodity DRAM parts and their replacement with parts that had compute capabilities. This is impossible. Adding compute to memory will make it more expensi
37.
by wtallis 2mo ago
It sounds like your complaint might be that it works poorly if you half-ass the localization process and assume that literal translation of strings is most or all of what localization means.
38.
by wtallis 2mo ago
I don't think that argument holds water, because the scope of what can be reasonably approximated by matrix multiplication is extremely broad (especially when the matrix multiplication is also paired with a source of randomness).
39.
by wtallis 2mo ago
Is this or any other SGX exploit a consequence of Intel processors not being open source?
40.
by wtallis 2mo ago
I wonder if the dislike comes from using third-party keyboards with excessively wide spacebars that make the modifier keys genuinely hard to reach with a thumb.
41.
by wtallis 2mo ago
It's been a long time since anyone tried to actually ship a chip with different instruction set support enabled across its cores, but Intel has spent the past several years shipping consumer parts where they had to disable some featu
42.
by wtallis 2mo ago
Did Intel ever ship any heterogeneous server parts? I'm not aware of any, and it looks like even the Raptor Lake desktop silicon sold under the Xeon brand only had P-cores enabled. The worst of Intel's processor core asymmetry was
43.
by wtallis 2mo ago
What degree of OS-indepedence do you think is reasonable to expect from a consumer-facing benchmark suite like Geekbench?
44.
by wtallis 2mo ago
Generally, yes. Most telemetry systems in software are not producing enough actionable insight to justify the privacy invasion. Spying on your customers on an opt-out basis just in case you one day come up with a use for that data is a wide
45.
by wtallis 2mo ago
So those generation numbers aren't really anchored to Apple's hardware designs. It's just counting from when Apple introduced the Metal API, and the first several generations were when the GPU cores Apple was using were still
46.
by wtallis 2mo ago
> failing after arbitrary timeouts introduces hard-to-debug failures under load What needs to fail here is the instruction doing insanely slow MMIO. That's not going to be too hard to debug; none of the examples of suitably slow ins
47.
by wtallis 2mo ago
This kind of age signalling with no verification whatsoever does not help the adtech companies at all.
48.
by wtallis 2mo ago
If anyone is distributing it within Illinois jurisdiction (or maybe even distributing it elsewhere while maintaining a business presence in Illinois), they could be at risk of qualifying as an operating system provider under Illinois law.
49.
by wtallis 2mo ago
I think it's pretty obvious that your explanation cannot be complete or accurate. Algorithmic feeds usually have a strong influence of what they want to show you , commonly pushing stuff you aren't interested in, or anything th
50.
by wtallis 2mo ago
I wonder whether a Thunderbolt accessory can cause arbitrarily long IO operations. What's the upper bound before some other layer gives up and causes the instruction to fault?
51.
by wtallis 2mo ago
None of what you said actually explains how HBM could require 3x the wafers. The base interface die has eight or 12 memory dies stacked on top of it. The wafer cost of that interface die is therefore small. If the process of die thinning an
52.
by wtallis 2mo ago
> (each HBM3 die is >1000mm² of silicon) Did you mean that each HBM3 stack is that large? Because it only takes one glance to see that the memory chips are much smaller than reticle-sized GPUs they sit next to.
53.
by wtallis 2mo ago
> who knows? You could try reading the footnotes, which include a link to https://www.amd.com/content/dam/amd/en/documents/solutions/a...
54.
by wtallis 2mo ago
In a hypothetical world where AMD wasn't allowed to do AMD64, and Intel stayed committed to Itanium: Itanium would still have sucked, and both PowerPC and SPARC would have out-sold Itanium by an even wider margin than they did in thi
55.
by wtallis 3mo ago
I've seen enough complaints about features like automatic emergency braking to be quite scared—not of the tech features, but of the drivers who are so overconfident that they are unwilling to accept any false positives from a safety fe
56.
by wtallis 3mo ago
Reads don't wear out flash memory to any meaningful extent.
57.
by wtallis 3mo ago
OEM versions of Windows are just copies with license terms dictating that they are to be installed on and tied to a specific new PC, as opposed to a full retail license that is not tied to a specific PC and may be transferred to a different
58.
by wtallis 3mo ago
AMD's Strix Halo has a 256-bit memory bus. Apple's Max class chips have a 512-bit memory bus, Ultra class chips have a 1024-bit memory bus. Unless you want to go for datacenter hardware, AMD's offerings simply aren't in
59.
by wtallis 3mo ago
LLM inference is a two-phase process. The first phase is prompt processing aka prefill. It's compute-heavy but requires relatively low memory bandwidth. The second phase is token generation aka decode, which doesn't require much i
60.
by wtallis 3mo ago
> A very frequent real-world workload is the compilation of a software project, which scales almost perfectly with the number of cores. Geekbench has that as a subtest. > For the other multi-threaded tasks, like running certain CAD&#x

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