sylware

4 ms·

31.
by sylware 1mo ago
The real core of the issue is actually the complexity/size and core design of media container/codec file formats.
32.
by sylware 1mo ago
Last time I read something about Zen6 it was 6GHz. So I guess the IBM stuff is "server slow" then. I wish RISC-V microarchitectures would get access to 2nm silicon processes, because RISC-V at 7GHz... yummy.
33.
by sylware 1mo ago
So why the 2nm x86 chips are clocked so low? Why couldn't they be 6GHz? x86_64 ISA did it again? That said IBM should add RISC-V support.
34.
by sylware 1mo ago
If Apple does design a RISC-V frontend to their MX microarchitecture... ARM better keep those ISA license fees close to zero.
35.
by sylware 1mo ago
lean from a technical point of view: size and complexity. That would include the SDK, namely the complexity of the syntax of used computer language (for instance excluding de facto c++ and similar), the build system, the amount of dependenc
36.
by sylware 1mo ago
Yep, you compare chips on the same level of silicon process. I was curious to see how far RISC-V still have to go from a microarchitecture stand point, but even in the same silicon process level, there are other things to take into account:
37.
by sylware 1mo ago
Wonder how it will fare when infering frontier models or 10T+ parameters. For coding, in order to get "quality" results, you will need those frontier models with their whole weights.
38.
by sylware 1mo ago
Missing the silicon process.
39.
by sylware 1mo ago
That's why _LEAN_ open source is really required, and that includes the SDK.
40.
by sylware 1mo ago
Maybe a Zen microarchitecture with a RISC-V/RVA front-end? While thinking about it, if NVIDIA or SAMSUNG go performant RISC-V CPU micro-architecture, will "probably" change the world.
41.
by sylware 1mo ago
Neural net maths are hardly above scientific high-school level.
42.
by sylware 2mo ago
Nah.. people will start to check for 'watermarks' first...
43.
by sylware 2mo ago
Indeed, if NVIDIA or SAMSUNG go super performant RISC-V implementations, things are very probably going to change.
44.
by sylware 2mo ago
In France, we have a bed story for children related to exactly that: "Pierre et le loup" (aka your "crying wolf"). It may be a EU wide tale.
45.
by sylware 2mo ago
Have a look at cproc/qbe, 70% of gcc -O3 speed (at the time I did CPU intensive benchmarks), for hardly a few % of gcc code. And it is not even using that grotesquely and absurdely complex c++ syntax.
46.
by sylware 2mo ago
Is fastmail blocking self-hosted SMTP servers without DNS like gmail.com? (email addresses with IP literals are stronger than SPF). Is fastmail gated with 'whatwg cartel' web engines like gmail.com?
47.
by sylware 2mo ago
Then RISC-V would need something like they did for open source software (in countries with barbaric IP), some sort of pool of defensive IP. Because, if you look at the current trajectory of RISC-V micro-architectures: they will be competi
48.
by sylware 2mo ago
Allright, you did describe a monstruous IP mine-field. No way anybody could reasonably use anything else than RISC-V.
49.
by sylware 2mo ago
So RISC-V is 'dragged down' because it cannot access the best silicon process (hardware big tech is hogging production capacity... how convenient...)
50.
by sylware 2mo ago
Then if I understood well what you said: the main bottleneck for many of those RISC-V microarchitectures is the access to the best silicon process. (ofc, they will have to optimize them for this node process)
51.
by sylware 2mo ago
All on latest silicon process?
52.
by sylware 2mo ago
I guess this would be orders of magnitude more horrible with x86_64?
53.
by sylware 2mo ago
Are they on the latest silicon process? Because, without neglecting the micro-architecture, we all know how critical the silicon process is for high-end performance.
54.
by sylware 2mo ago
This guy is weird: there is no perfect ISA, only compromises and tradeoffs. He is looking for _his_ perfect. Won't happen, unless lucky, namely your perfect aligns with RISC-V tradeoffs. There are also sweet spots, and I am writting RI
55.
by sylware 2mo ago
You would need a massive amount of claude output beyond anything humanly reasonably to train a model. Namely, consuming a lot of inference resources. If you don't do that at those scale, the training will probably be quite inefficient
56.
by sylware 2mo ago
Then a whole industry will rise at tracking and removing those watermarks.
57.
by sylware 2mo ago
Yep, AI freedom of usage will only happen locally. Remotely, "That's all folks", The End.
58.
by sylware 2mo ago
Indeed, Linus T. is not superman, he cannot preserve linux of all the danger around.
59.
by sylware 2mo ago
doh! (all that said, I don't know of anyone who would answer an unknown number call)
60.
by sylware 2mo ago
As far as I know, that was for x86(32bits) linux, that decades ago. With those assembly source files (which do not abuse any pre-processor) and plain and simple C, I could build a modern x86_64 linux kernel with cproc/qbe (which gets 7

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