solarexplorer

11 ms·

91.
by solarexplorer 12y ago
A flag register is indeed an additional dependency and may end up in the critical path. But x86 and ARM already have a flag register. They already pay the cost. And you don't need a flag resister to check for overflows. Trap on overflo
92.
by solarexplorer 12y ago
Good point. So then instead of updating Q out-of-order you could update at commit. You just need to block any instruction that reads Q until the OoO core is empty. This is _much_ cheaper to implement than adding a dependency on all instruct
93.
by solarexplorer 12y ago
The sticky overflow bit is useful when you do signal processing with integers. To detect bugs it would be better to have a real exception that indicates which instruction caused the overflow. But to do that you would have to change/ext
94.
by solarexplorer 12y ago
Yes, AMD should have added it to x64. It isn't exactly new either. The Alpha's integer instructions had a bit in the instruction word that indicated if an overflow should cause a trap or not. IMHO that is the ideal solution.
95.
by solarexplorer 12y ago
If you assume that reading (and clearing) the Q bit is infrequent, you can do something much cheaper. Because the bit is sticky, the order in which you set it does not matter. And when you need to read (or to clear) the Q bit, you just bloc
96.
by solarexplorer 12y ago
PDF on CiteSeer: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.41....
97.
by solarexplorer 12y ago
IIRC a single DDR3 slot can address max 8GBytes. So the driver will have to map the 400GB Flash into this window.
98.
by solarexplorer 12y ago
SMT maps multiple threads to a single core. This maps a single thread to multiple cores.
99.
by solarexplorer 12y ago
Also nice: "can't happen" https://github.com/search?utf8=✓&q=%22can%27t+happen%22&type... From the Jargon file: can't happen The traditional program comment for code executed under a condition
100.
by solarexplorer 12y ago
You may want to send your syslog to the remote server too. Like patio11 said, after the web server gets hacked, you cannot trust it anymore to do a legit git diff or store the legit log files. If you have a remote syslog, you can at least d
101.
by solarexplorer 12y ago
OK, I see your point. Of course, the type system will not substitute this kind of tests. But it allows you to check the whole range of values. This is helpful if you e.g. wanted to handle overflows, wanted to limit the operands to positive
102.
by solarexplorer 12y ago
Well, types are essentially sets of values. So if you can capture the values that you expect in a type, then the type system _does_ give you a guarantee.
103.
by solarexplorer 12y ago
We are in violent agreement here. My point was just to note that the author apparently did not understand the difference between Dhrystone MIPS and "real" MIPS. He probably also did not understand that Dhrystone is an ancient benc
104.
by solarexplorer 12y ago
From the article: "Keep in mind that these processors use different instruction sets (ISAs) so DMIPS are not directly comparable." But DMIPS doesn't refer to million instructions per second, but to the relative performance fo
105.
by solarexplorer 12y ago
I think the point is not so much that RISC-V is better than x86 or that RISC-V with the same budget would be better than x86, etc. The point is that since RISC-V so simple, that you can produce _your_own_ customized cpus with a very small b
106.
by solarexplorer 12y ago
And a good example is probably Google ranking...
107.
by solarexplorer 12y ago
That depends on your definition of "seriously" I guess. But there is no need to stop at the plastic. Have a look what the guys at chipworks are doing: http://www.chipworks.com Also the Russians are traditionally quite
108.
by solarexplorer 12y ago
Not necessarily. I had my bike stolen in Germany and reported the serial # to the police. A few years later they called me to return me my bike. So they obviously have some sort of database. I don't know if it's just for the town
109.
by solarexplorer 12y ago
Traffic shaping shaping implies dropping packets. You could try to buffer some of them to send them later when bandwidth is available, but you would run out of buffer space very quickly. Buffering and flow control is best left to the endpoi
110.
by solarexplorer 12y ago
Yes, Cocoa is very complex. But I hope that a language like Swift will make it easier to come up with high level libraries that hide some of that complexity. We'll see what happens. Personally I feel that with Swift instead of Objectiv
111.
by solarexplorer 12y ago
You mean manufacturers want to avoid legal action when they break their own specs? They already did, the paper contains an example. The point of an architecture specification is not to dictate a specific hardware implementation, but to esta
112.
by solarexplorer 12y ago
Memory ordering specs are a minefields. I commend the authors for demanding formal specifications from the manufacturers. But I don't think that the solution is to come up with new alternative specs line x86-TSO. It is the manufacturer
113.
by solarexplorer 12y ago
Yep. Thank you.
114.
by solarexplorer 12y ago
I don't get it. "Similar numbers" but "significantly worse"? You measure performance and compile without optimization?! If you have better numbers, please share them!
115.
by solarexplorer 12y ago
To the contrary, out-of-order execution and speculative execution make precise exceptions trivial to support. As long as exceptions are not frequent, there is no performance pentalty either. It's the older in-order pipelines who strugg
116.
by solarexplorer 12y ago
Keeping the complex stuff out of the kernel is good advice. (and not just during development)
117.
by solarexplorer 12y ago
A very nice book on the topic is Elias Canetti's Crowds and Power (Masse und Macht). Canetti won the Nobel Prize in Literate and writes very well. http://en.wikipedia.org/wiki/Crowds_and_Power http://de
118.
by solarexplorer 12y ago
Sure, you can do floating point in software. My point is that dedicated hardware is very likely more power efficient at it. The same goes for memory: accesses to off-chip memory cost much more energy than accesses to on-chip memory. It woul
119.
by solarexplorer 12y ago
The assembly subroutine is not optimal because the compiler can not inline it. A ASM expression [1] is much better. Also, it is weird to write the result to memory just to avoid to repeat the addition. A memory operation is quite complex, b
120.
by solarexplorer 12y ago
What would be the point for Google to build their own CPU? How would it be different from what IBM has to offer?

More ›