rrss

27 ms·

241.
by rrss 6y ago
In my interpretation, "dedicated hardware for things like MP3s" doesn't necessarily mean "hardware MP3 decoding." Intel MMX (multimedia extensions) introduced dedicated hardware to accelerate things like MP3 decodin
242.
by rrss 6y ago
There are similar basins in Europe, probably similarly suitable. https://en.wikipedia.org/wiki/Permian_Basin_(Europe) https://en.wikipedia.org/wiki/North_German_basin
243.
by rrss 6y ago
How is that video inconsistent with j-pb's comment? The video describes what happened, and summarizes the cause as: > Basically, the entire system was ill-prepared for a storm of this magnitude. The video addresses only what happene
244.
by rrss 6y ago
> Isn't really a think when we thing about the time scale of nuclear waste... it is. drill a few miles down into the miles-thick crystalline salt in the permian basin. it will not go anywhere for millions of years.
245.
by rrss 6y ago
The A64fx also has hardware synchronization barriers to synchronize cores, which is a pretty GPU-like thing (at least it is very common on GPUs, and rare on CPUs). https://github.com/fujitsu/A64FX/blob/master&
246.
by rrss 6y ago
nope, hardware vendors have been introducing artificial restrictions in some products for market segmentation for decades e.g. ECC support in CPUs, mods to turn radeon into firegl / geforce into quadro, fused off cores
247.
by rrss 6y ago
lol, this is such a vacuous comment. "device made specifically for gaming is not useful for people uninterested in gaming"
248.
by rrss 6y ago
> Software people often don't know about the distinction, and use the terms interchangeably I think YMMV here - in my experience, only (some) software people make this distinction, and hardware people use the terms interchangeably.
249.
by rrss 6y ago
Yes, they did. Intel's implementation of checking permissions in parallel with speculative loads was vulnerable because the transient effects could be observed through cache timing information. All of these attacks, meltdown included,
250.
by rrss 6y ago
Ok, but "Intel fail" indicates meltdown was specific to Intel processors, when it was also present of IBM and some Arm designs.
251.
by rrss 6y ago
my memory is that the some of the Intel and AMD architecture extensions (including the various virtualization extensions) are incompatible.
252.
by rrss 6y ago
I don't think this is a particularly accurate description of pytorch in 2021. Yeah, the original c++ backend came from torch, but I think most of that has been replaced. AFAIK, all the development of the c++ backend for pytorch over th
253.
by rrss 6y ago
Rocketlab does have "real world results" - they've launched customer payloads to orbit 18 times in the last few years. AFAIK, blue origin has not achieved orbit, and virgin orbit is still doing (years-delayed?) demonstration
254.
by rrss 6y ago
pytorch can use more than one core.
255.
by rrss 6y ago
The author has a comment here describing what that would take: https://github.com/vosen/ZLUDA/issues/17#issuecomment-735403... . tl;dr: someone would need to re-implement cuDNN
256.
by rrss 6y ago
No. You can't even do that in a desktop. AMD and Intel CPUs don't use the same socket or pinout.
257.
by rrss 6y ago
(regardless of the answer, you should update the link to point to the original source, per site guidelines)
258.
by rrss 6y ago
Did you get permission from SemiEngineering to reprint their article in full on your site?
259.
by rrss 6y ago
original: https://semiengineering.com/breaking-the-2nm-barrier/
260.
by rrss 6y ago
This certainly wins for lowest cost, but I don't think it wins for lowest environmental impact - the spares reduce much of the benefit If the author makes it to 10 years with these 3 laptops from 2006, it will add 3.3 years of lifespan
261.
by rrss 6y ago
A product performs worse at some stuff than it might have in a hypothetical reality, and it says so on the box. What should be illegal about this, and why?
262.
by rrss 6y ago
Wouldn't the easy money grab be to just set MSRP for all cards way higher ($5k?) while the demand is ~infinite?
263.
by rrss 6y ago
because building 8nm semiconductor fabs is slightly harder than setting up a lemonade stand.
264.
by rrss 6y ago
I don't think the c standard specifies this behavior. malloc must return either a pointer where you can store an object, or null. I think platform details about when accesses to that pointer might fail are outside the scope of the lang
265.
by rrss 6y ago
googling "softbank stake in nvidia" gives me "SoftBank Sells Entire Nvidia Stake" from 2019: https://www.wsj.com/articles/softbank-sells-entire-nvidia-st... Is your information about SoftBank being
266.
by rrss 6y ago
This article has a pretty good overview of the situation and other metrics that actually track progress: https://spectrum.ieee.org/semiconductors/devices/a-better-wa...
267.
Fujitsu A64FX Microarchitecture Manual [pdf](github.com)
73 points by rrss 6y ago|52 comments
268.
by rrss 6y ago
I would guess yes, but don't really have any idea. To clarify, though, the changes introduced in newer SIMD extensions are rarely just a width increase. AVX-512, for example, increased the width from 256-bit to 512-bit, but also brough
269.
by rrss 6y ago
I think you've misunderstood my comment. Obviously I am not arguing that apple doesn't know what they are doing. The article suggested that ARM announced that architecture licensees can add instructions to ARMv8-A, which isn'
270.
by rrss 6y ago
Generally the idea is to make the instruction set "scalable," such that if the CPU's vector ALU doubles in width, applications don't need to be rewritten or recompiled to benefit. (In contrast to existing SIMD instructio

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